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Text File | 1995-01-29 | 200.9 KB | 4,852 lines

▄▄▄▄ ▄▄▄▄ █ █ █ █▄▄▄▄▄ ▄▄▄ ▄ ▄ ▄▄▄▄ ▄▄▄▄ █▄▄▄█▄ ▄ ▄▄▄ ▄▄▄▄▄ ▄▄▄▄▄▄ ▄▄▄▄▄ ▄▄▄▄ █ █ █ █ █ █ █ █ █ █ █ █ █▄▄▄█ █▄▄▄▄ █ █▄▄ █▄▄▄▀ █ █ █ █ █ █ █ █ █ █ █ █ █ █ █ █ █ █ █ ▀▀▀▀▀▀ ▀▀▀▀▀ ▀▀▀▀ ▀ ▀ ▀▀▀▀ ▀▀▀▀▀▀ ▀▀▀▀▀ ▀ ▀ ▀▀▀▀▀ ▀ ▀▀▀▀▀ ▀ ▀ Programming Information v0.90 January 29, 1995 André Baresel - Craig Jackson Copyright (c) 1995 ============================================================================== DISCLAIMER ------------------------------------------------------------------------------ ALL INFORMATION IN THIS DOCUMENT WAS OBTAINED FROM NON-CONFIDENTIAL, PUBLIC DOMAIN, SOURCES AND LEGAL INVESTIGATION BY THE AUTHORS. APART FROM CASUAL EXAMININATION OF THE SOUNDBLASTER OWNER'S MANUALS, ABSOLUTELY NO REFERENCE WAS MADE TO CREATIVE LABS DOCUMENTATION INCLUDING, BUT NOT LIMITED TO, SOFTWARE DEVELOPMENT KITS, PROGRAMMING NOTES, AND SOURCE CODE. THIS DOCUMENT IS NEITHER GUARANTEED TO BE FIT FOR ANY PARTICULAR PURPOSE NOR TO BE ENTIRELY CORRECT. LIABILITY RESTS WITH THE USER OF THE DOCUMENTATION IF AND WHEN INFORMATION CONTAINED HEREIN RESULTS DIRECTLY OR INDIRECTLY IN LOSS OF PROFITS, PRODUCTIVITY, OR SLEEP. ABSOLUTELY NO WARRANTIES OR GUARANTIES, EITHER EXPRESSED OR IMPLIED, ACCOMPANY THIS DOCUMENT. THIS DOCUMENT, ITS AUTHORS, AND CONTRIBUTORS CLAIM NO AFFILIATION WITH CREATIVE LABS NOR DO THEY NECESSARILY ENDORSE ANY OF THE COMPANIES OR PRODUCTS MENTIONED. THIS DOCUMENT IS FREELY REDISTRIBUTABLE ONLY IN ITS ORIGINAL UNMODIFIED FORM AND PROVIDED NO DIRECT PROFIT IS MADE FROM ITS DISTRIBUTION. ALL COPYRIGHTS AND TRADEMARKS BELONG TO THEIR RESPECTIVE OWNERS. ============================================================================== SOUNDBLASTER MODELS ------------------------------------------------------------------------------ SoundBlaster 1.0 SoundBlaster 1.5 SoundBlaster 2.0 SoundBlaster MCV (MCA) SoundBlaster Pro SoundBlaster Pro2 SoundBlaster Pro Value Edition SoundBlaster Pro MCV (MCA) SoundBlaster 16 SoundBlaster 16 Basic Edition SoundBlaster 16 Value Edition SoundBlaster 16 ASP SoundBlaster 16 MultiCD SoundBlaster 16 MultiCD ASP SoundBlaster 16 SCSI-2 SoundBlaster 16 SCSI-2 ASP SoundBlaster AWE32 SoundBlaster AWE32 Value Edition ╔═══════════════════════╤═══════════════════╤═══════════════════╗ ║ SOUNDBLASTER MODEL │ 8-BIT Hz (DAC) │ 16-BIT Hz (DAC) ║ ║ │ MONO │ MONO ║ ╠═══════════════════════╪═══════════════════╪═══════════════════╣ ║ SoundBlaster 1.x │ 4000-22222 │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster 2.x │ 4000-45454 │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster Pro │ 4000-45454 │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster 16 │ 4000-45454 │ 4000-45454 ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster AWE32 │ 5000-45454 │ 5000-45454 ║ ╚═══════════════════════╧═══════════════════╧═══════════════════╝ ╔═══════════════════════╤═══════════════════╤═══════════════════╗ ║ SOUNDBLASTER MODEL │ 8-BIT Hz (DAC) │ 16-BIT Hz (DAC) ║ ║ │ STEREO │ STEREO ║ ╠═══════════════════════╪═══════════════════╪═══════════════════╣ ║ SoundBlaster 1.x │ N/A │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster 2.x │ N/A │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster Pro │ 4000-22727 │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster 16 │ 4000-45454 │ 4000-45454 ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster AWE32 │ 5000-45454 │ 5000-45454 ║ ╚═══════════════════════╧═══════════════════╧═══════════════════╝ ╔═══════════════════════╤═══════════════════╤═══════════════════╗ ║ SOUNDBLASTER MODEL │ 8-BIT Hz (ADC) │ 16-BIT Hz (ADC) ║ ║ │ MONO │ MONO ║ ╠═══════════════════════╪═══════════════════╪═══════════════════╣ ║ SoundBlaster 1.x │ 4000-11111 │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster 2.x │ 4000-15151 │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster Pro │ 4000-45454 │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster 16 │ 4000-45454 │ 4000-45454 ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster AWE32 │ 5000-45454 │ 5000-45454 ║ ╚═══════════════════════╧═══════════════════╧═══════════════════╝ ╔═══════════════════════╤═══════════════════╤═══════════════════╗ ║ SOUNDBLASTER MODEL │ 8-BIT Hz (ADC) │ 16-BIT Hz (ADC) ║ ║ │ STEREO │ STEREO ║ ╠═══════════════════════╪═══════════════════╪═══════════════════╣ ║ SoundBlaster 1.x │ N/A │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster 2.x │ N/A │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster Pro │ 4000-22727 │ N/A ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster 16 │ 4000-45454 │ 4000-45454 ║ ╟───────────────────────┼───────────────────┼───────────────────╢ ║ SoundBlaster AWE32 │ 5000-45454 │ 5000-45454 ║ ╚═══════════════════════╧═══════════════════╧═══════════════════╝ ============================================================================== SOUNDBLASTER COMPATIBLES ------------------------------------------------------------------------------ ??? AudioDrive 688 ??? Laserwave Supra 16 ??? MediaConcept Pro Adaptec Audio Machine??? Addonics??? Sound Master Add Tech Sound 2000 Advanced Gravis Gravis Ultrasound Gravis Ultrasound MAX Alpha Systems VR ATI ATI Stereo F/X AVM Technology AltraPro Aztech Sound Galaxy??? Sound Galaxy BXII Sound Galaxy BXII Extra Sound Galaxy Basic 16 Sound Galaxy Basic 16 Extra Sound Galaxy Nova 16 Sound Galaxy NXII Sound Galaxy NX Pro Sound Galaxy Orion 16 Sound Galaxy Pro??? Sound Galaxy Pro 16 Biostar??? MediaChips Audio Device 16 (7168VMD) Bluepoint Sound FX 3000??? Cardinal Technologies Digital Sound Pro 16 Sound Pilot Computer Peripherals ViVa Maestro 16 ViVa Maestro 16 VR CPS AudioBlaster 1.0 AudioBlaster 1.5 AudioBlaster 2.0 AudioBlaster 2.5 AudioBlaster 4.0 Diamond Sonic Sound Sonic Sound LX DSP Solutions PORT*ABLE Sound Plus Ensoniq Ensoniq Soundscape Gallant Audio Plus True 16 Genoa Systems AudioBahn 16 Pro IBM IBM Windsurfer Kingston Technologies Omnivox Logitech Inc. Soundman 16 Soundman Wave Lyben Sound Card Basic Sound Card 16 Stereo MediaMagic OnMagic??? MediaTrix AudioTrix Pro MediaVision Deluxe Premium 3D Premium 3D MultiCD Premium 3D SCSI-2 Pro 3D Pro Audio 16 Basic Pro Audio Spectrum 16 Pro Audio Studio Pro Sonic 16 MEI Premium 16 Sound Card Microsoft Windows Sound System 2.0??? MultiWave Innovation Inc. AudioWave Platinum 16 Nu Reality Vivid 3D??? Oak Technologies Mozart-128 Orchid GameWave 32 Sound Producer SoundWave 32 Paradise Audio Basic Audio Professional ProLink Computer Inc. SoundPlus Prometheus Aria 16 Aria 16se Reveal Sound FX/32 Wavetable (SC600) Sigma Designs Reel Magic Triumph Logistic Computers Audio Forge Professional Trust Sound Expert 16 Deluxe Turtle Beach Monte Carlo Tropez Yamaha Yamaha CBX-B1 Zoltrix TESS ============================================================================== ENVIRONMENT VARIABLE ------------------------------------------------------------------------------ BLASTER=Aa Ii Dd Hh Pp Tt Aa - Base Address 0210h, 0220h, 0230h, 0240h, 0250h, 0260h, 0280h Ii - Interrupt Request 2, 3, 5, 7, 10 Dd - DMA Channel, 8-bit 0, 1, 3 Hh - DMA Channel, 16-bit 5, 6, 7 Pp - Base MIDI Address 0300h, 0330h Tt - Model 1(1.x), 2(Pro), 3(2.0), 4(Pro2.0), 5(ProMCV), 6(16, AWE32) NOTE: 16-bit DMA definition may actually refer to an 8-bit DMA alias. ============================================================================== HARDWARE PORTS ------------------------------------------------------------------------------ 02x00h C/MS 1-6 - Data Port Write SB Only 02x00h FM Music - Left Status Port Read SBPro 02x00h FM Music - Left Register Port Write SBPro 02x01h C/MS 1-6 - Register Port Write SB Only 02x01h FM Music - Left Data Register Write SBPro 02x02h C/MS7-12 - Data Port Write SB Only 02x02h FM Music - Right Status Port Read SBPro 02x02h FM Music - Right Register Port Write SBPro 02x03h C/MS7-12 - Register Port Write SB Only 02x03h FM Music - Right Data Register Write SBPro 02x04h Mixer - Register Port Write SBPro 02x05h Mixer - Data Register Read/Write SBPro 02x06h DSP - Reset Write SB 02x08h FM Music - Compatible Status Port Read SB 02x08h FM Music - Compatible Register Port Write SB 02x09h FM Music - Compatible Data Register Write SB 02x0Ah DSP - Read Data Read SB 02x0Ch DSP - Write Data or Command Write SB 02x0Ch DSP - Write Buffer Status Read SB 02x0Dh DSP - Timer Interrupt Clear Read SB16??? 02x0Eh DSP - Data Available Status Read SB 02x0Eh DSP - IRQ Acknowledge, 8-bit Read SB 02x0Fh DSP - IRQ Acknowledge, 16-bit Read SB16 02x10h CD-ROM - Data Register Read SBPro 02x10h CD-ROM - Command Port Write SBPro 02x11h CD-ROM - Status Port Read SBPro 02x12h CD-ROM - Reset Write SBPro 02x13h CD-ROM - Enable Write SBPro 0388h AdLib - Status Port Read SB 0388h AdLib - Register Port Write SB 0389h AdLib - Data Register Write SB 038Ah Advanced AdLib - Status Port Read SB16 038Ah Advanced AdLib - Register Port Write SB16 038Bh Advanced AdLib - Data Register Write SB16 03x00h MPU-401 - Data Port Read/Write SB16??? 03x01h MPU-401 - Status Port Read SB16??? 03x01h MPU-401 - Command Port Write SB16??? 0200h-0207h Joystick Varies SB ------------------------------------------------------------------------------ 02x00h C/MS - Data Port (Voice 1-6) Write SB Only DESCRIPTION References currently selected C/MS voice 1-6 index register. PROCEDURE a) Write register index (02x01h) b) Write register data (02x00h) SEE ALSO 02x01h C/MS - Register Port (Voice 1- 6) Write ····················································· 02x02h C/MS - Data Port (Voice 7-12) Write ------------------------------------------------------------------------------ 02x00h FM Music - Left Status Port Read SBPro DESCRIPTION Categorizes left-channel synthesizer generated timer interrupts. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (1) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┘ │ │ └─────────────────────── Timer 2 Status (1 = Expired) │ └─────────────────────────── Timer 1 Status (1 = Expired) └─────────────────────────────── Global Timer Status (1 = Active ) NOTES ■ Global Timer Status will be active if either timer has expired. ■ Counter period of Timer 1 is 80µs, and Timer 2 is 230µs. ■ Synthesizer generated timer interrupts are signalled on IRQ0. SEE ALSO 02x00h FM Music - Left Register Port Write 02x01h FM Music - Left Data Register Write ····················································· 02x08h FM Music - Compat. Status Port Read 0338h AdLib - Status Port Read ····················································· 02x02h FM Music - Right Status Port Read ------------------------------------------------------------------------------ 02x00h FM Music - Left Register Port Write SBPro DESCRIPTION Selects register index into left-channel synthesizer data port (02x01h) PROCEDURE a) Write register index (02x00h) b) Wait 3.3µs (0.0?µs OPL3) c) Write register data (02x01h) d) Wait 23µs (0.28µs OPL3) NOTES ■ Original SoundBlaster Pros were equipped with dual OPL2 synthesizers, connecting this channel to the left speaker exclusively; whereas later models began using OPL3-compatible synthesizers, which send all output to both the left and right speakers unless programmed to do otherwise. SEE ALSO 02x00h FM Music - Left Status Port Read 02x01h FM Music - Left Data Register Write ····················································· 02x08h FM Music - Compat. Register Port Write 0338h AdLib - Register Port Write ····················································· 02x02h FM Music - Right Register Port Write ------------------------------------------------------------------------------ 02x01h C/MS - Register Port (Voice 1-6) Write SB Only DESCRIPTION Selects register index into C/MS voice 1-6 data port (02x00h) PROCEDURE a) Write register index (02x01h) b) Write register data (02x00h) SEE ALSO 02x00h C/MS - Data Port (Voice 1- 6) Write ····················································· 02x03h C/MS - Register Port (Voice 7-12) Write ------------------------------------------------------------------------------ 02x01h FM Music - Left Data Register Write SBPro DESCRIPTION References currently selected left-channel synthesizer index register. PROCEDURE a) Write register index (02x00h) b) Wait 3.3µs (0.0?µs OPL3) c) Write register data (02x01h) d) Wait 23µs (0.28µs OPL3) NOTES ■ Original SoundBlaster Pros were equipped with dual OPL2 synthesizers, connecting this channel to the left speaker exclusively; whereas later models began using OPL3-compatible synthesizers, which send all output to both the left and right speakers unless programmed to do otherwise. SEE ALSO 02x00h FM Music - Left Status Port Read 02x00h FM Music - Left Register Port Write ····················································· 02x09h FM Music - Compat. Data Register Write 0339h AdLib - Data Register Write ····················································· 02x03h FM Music - Right Data Register Write ------------------------------------------------------------------------------ 02x02h C/MS - Data Port (Voice 7-12) Write SB Only DESCRIPTION References currently selected C/MS voice 7-12 index register. PROCEDURE a) Write register index (02x03h) b) Write register data (02x02h) SEE ALSO 02x03h C/MS - Register Port (Voice 7-12) Write ····················································· 02x00h C/MS - Data Port (Voice 1- 6) Write ------------------------------------------------------------------------------ 02x02h FM Music - Right Status Port Read SBPro DESCRIPTION Categorizes right-channel synthesizer generated timer interrupts. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (1) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┘ │ │ └─────────────────────── Timer 2 Status (1 = Expired) │ └─────────────────────────── Timer 1 Status (1 = Expired) └─────────────────────────────── Global Timer Status (1 = Active ) NOTES ■ Global Timer Status will be active if either timer has expired. ■ Counter period of Timer 1 is 80µs, and Timer 2 is 230µs. ■ Synthesizer generated timer interrupts are signalled on IRQ0. SEE ALSO 02x02h FM Music - Right Register Port Write 02x03h FM Music - Right Data Register Write ····················································· 038Ah A. Adlib - Status Port Read ····················································· 02x00h FM Music - Left Status Port Read ------------------------------------------------------------------------------ 02x02h FM Music - Right Register Port Write SBPro DESCRIPTION Selects register index into right-channel synthesizer data port (02x03h) PROCEDURE a) Write register index (02x02h) b) Wait 3.3µs (0.0?µs OPL3) c) Write register data (02x03h) d) Wait 23µs (0.28µs OPL3) NOTES ■ Original SoundBlaster Pros were equipped with dual OPL2 synthesizers, connecting this channel to the right speaker exclusively; whereas later models began using OPL3-compatible synthesizers, which send all output to both the left and right speakers unless programmed to do otherwise. SEE ALSO 02x02h FM Music - Right Status Port Read 02x03h FM Music - Right Data Register Write ····················································· 038Ah A. Adlib - Register Port Write ····················································· 02x00h FM Music - Left Register Port Write ------------------------------------------------------------------------------ 02x03h C/MS - Register Port (Voice 7-12) Write SB Only DESCRIPTION Selects register index into C/MS voice 7-12 data port (02x02h) PROCEDURE a) Write register index (02x03h) b) Write register data (02x02h) SEE ALSO 02x02h C/MS - Data Port (Voice 7-12) Write ····················································· 02x01h C/MS - Register Port (Voice 1- 6) Write ------------------------------------------------------------------------------ 02x03h FM Music - Right Data Register Write SBPro DESCRIPTION References currently selected right-channel synthesizer index register. PROCEDURE a) Write register index (02x02h) b) Wait 3.3µs (0.0?µs OPL3) c) Write register data (02x03h) d) Wait 23µs (0.28µs OPL3) NOTES ■ Original SoundBlaster Pros were equipped with dual OPL2 synthesizers, connecting this channel to the right speaker exclusively; whereas later models began using OPL3-compatible synthesizers, which send all output to both the left and right speakers unless programmed to do otherwise. SEE ALSO 02x02h FM Music - Right Status Port Read 02x02h FM Music - Right Register Port Write ····················································· 038Bh A. Adlib - Data Register Write ····················································· 02x01h FM Music - Left Data Register Write ------------------------------------------------------------------------------ 02x04h Mixer - Register Port Write SBPro DESCRIPTION Selects register index into mixer data port (02x05h) SELECTION BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Mixer Register Index bit 0 (SB16) │ │ │ │ │ │ └─────┬─ Mixer Register Index bit 3-1 (SBPro) │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────── Mixer Register Index bit 4 (SB16) │ │ └─────────────────────┬─ Mixer Register Index bit 7-5 (SBPro) │ └─────────────────────────┤ └─────────────────────────────┘ PROCEDURE a) Write mixer index (02x04h) b) Read/write mixer data (02x05h) NOTES ■ See complete mixer reference later in this document. ■ MediaVision 3D-series cards use this port for index and data output. SEE ALSO 02x05h Mixer - Data Register Read/Write ------------------------------------------------------------------------------ 02x05h Mixer - Data Register Read/Write SBPro DESCRIPTION References currently selected mixer index register. PROCEDURE a) Write mixer index (02x04h) b) Read/write mixer data (02x05h) NOTES ■ See complete mixer reference later in this document. SEE ALSO 02x05h Mixer - Register Port Write ------------------------------------------------------------------------------ 02x06h DSP - Reset Write SB DESCRIPTION Performs complete reset of DSP, terminating all pending operations. PROCEDURE a) Write 001h b) Wait 3.3µs minimum c) Write 000h d) Wait 100µs maximum for DSP Data Available (02x0Eh) e) Read 0AAh from DSP Read Data (02x0Ah) NOTES ■ Reset of DSP disables speaker (see DSP command 0D3h). ------------------------------------------------------------------------------ 02x08h FM Music - Compatible Status Port Read SB DESCRIPTION Categorizes left-channel synthesizer generated timer interrupts. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (1) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┘ │ │ └─────────────────────── Timer 2 Status (1 = Expired) │ └─────────────────────────── Timer 1 Status (1 = Expired) └─────────────────────────────── Global Timer Status (1 = Active ) NOTES ■ Global Timer Status will be active if either timer has expired. ■ Counter period of Timer 1 is 80µs, and Timer 2 is 230µs. ■ Synthesizer generated timer interrupts are signalled on IRQ0. ■ Alias for FM Music - Left Status Port (02x00h) on SBPro or higher. SEE ALSO 02x08h FM Music - Compat. Register Port Write 02x09h FM Music - Compat. Data Register Write ····················································· 02x00h FM Music - Left Status Port Read ------------------------------------------------------------------------------ 02x08h FM Music - Compatible Register Port Write SB DESCRIPTION Selects register index into left-channel synthesizer data port (02x09h) PROCEDURE a) Write register index (02x08h) b) Wait 3.3µs (0.0?µs OPL3) c) Write register data (02x09h) d) Wait 23µs (0.28µs OPL3) NOTES ■ Original SoundBlaster Pros were equipped with dual OPL2 synthesizers, connecting this channel to the left speaker exclusively; whereas later models began using OPL3-compatible synthesizers, which send all output to both the left and right speakers unless programmed to do otherwise. ■ Alias for FM Music - Left Register Port (02x00h) on SBPro or higher. SEE ALSO 02x08h FM Music - Compat. Status Port Read 02x09h FM Music - Compat. Data Register Write ····················································· 02x00h FM Music - Left Register Port Write ------------------------------------------------------------------------------ 02x09h FM Music - Compatible Data Register Write SB DESCRIPTION References currently selected left-channel synthesizer index register. PROCEDURE a) Write register index (02x08h) b) Wait 3.3µs (0.0?µs OPL3) c) Write register data (02x09h) d) Wait 23µs (0.28µs OPL3) NOTES ■ Original SoundBlaster Pros were equipped with dual OPL2 synthesizers, connecting this channel to the left speaker exclusively; whereas later models began using OPL3-compatible synthesizers, which send all output to both the left and right speakers unless programmed to do otherwise. ■ Alias for FM Music - Left Data Register (02x01h) on SBPro or higher. SEE ALSO 02x08h FM Music - Compat. Status Port Read 02x08h FM Music - Compat. Register Port Write ····················································· 02x01h FM Music - Left Data Register Write ------------------------------------------------------------------------------ 02x0Ah DSP - Read Data Read SB DESCRIPTION Input port for DSP data byte reads. PROCEDURE a) Loop until bit 7 = 1 of DSP Data Available Status (02x0Eh read) b) Input byte from DSP Read Data port (02x0Ah read) NOTES ■ Hard system resets occasionally cause some DSPs to leave an extraneous data byte on the bus (typically 0AAh). Perform an explicit DSP reset at application startup to correct for this. SEE ALSO 02x0Eh DSP - Data Available Status Read ····················································· 02x0Ch DSP - Write Data or Command Write ····················································· 02x06h DSP - Reset Write ---------------------------------------------------------------------------- 02x0Ch DSP - Write Data or Command Write SB DESCRIPTION Output port for DSP command and data byte writes. PROCEDURE a) Loop until bit 7 = 0 of DSP Write Buffer Status (02x0Ch read) b) Output byte to DSP Write Data or Command port (02x0Ch write) SEE ALSO 02x0Ch DSP - Write Buffer Status Read ····················································· 02x0Ah DSP - Read Data Read ------------------------------------------------------------------------------ 02x0Ch DSP - Write Buffer Status Read SB DESCRIPTION Indicates whether or not DSP is ready to receive data through the DSP Write Data or Command port (02x0Ch write). STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │[6]│[5]│[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (?) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┘ └─────────────────────────────── Write Buffer Status (0 = Ready) PROCEDURE a) Loop until bit 7 = 0 of DSP Write Buffer Status (02x0Ch read) b) Output byte to DSP Write Data or Command port (02x0Ch write) SEE ALSO 02x0Ch DSP - Write Data or Command Write ····················································· 02x0Eh DSP - Data Available Status Read ------------------------------------------------------------------------------ 02x0Dh DSP - Timer Interrupt Clear Read SB16??? ??? ------------------------------------------------------------------------------ 02x0Eh DSP - Data Available Status Read SB DESCRIPTION Indicates whether or not DSP has pending data to be read through the DSP Read Data port (02x0Ah read). STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │[6]│[5]│[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (?) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┘ └─────────────────────────────── Read Status (1 = Ready) PROCEDURE a) Loop until bit 7 = 1 of DSP Data Available Status (02x0Eh read) b) Input byte from DSP Read Data port (02x0Ah read) SEE ALSO 02x0Ah DSP - Read Data Read ····················································· 02x0Ch DSP - Write Buffer Status Read ------------------------------------------------------------------------------ 02x0Eh DSP - IRQ Acknowledge, 8-bit Read SB DESCRIPTION Acknowledges an IRQ signalled by an 8-bit DSP operation. PROCEDURE a) IRQ: Read from IRQ Acknowledge, 8-bit port (02x0Eh) b) IRQ: Perform Generic EOI (020h) to appropriate PICs NOTES ■ Reflects correct DSP Data Available Status from IRQ. SEE ALSO 02x0Fh DSP - IRQ Acknowledge, 16-bit Read ------------------------------------------------------------------------------ 02x0Fh DSP - IRQ Acknowledge, 16-bit Read SB16 DESCRIPTION Acknowledges an IRQ signalled by an 16-bit DSP operation. PROCEDURE a) IRQ: Read from IRQ Acknowledge, 16-bit port (02x0Fh) b) IRQ: Perform Generic EOI (020h) to appropriate PICs NOTES ■ Still used for aliased 16-bit DMA (see mixer register 081h) SEE ALSO 02x0Eh DSP - IRQ Acknowledge, 8-bit Read ------------------------------------------------------------------------------ 02x10h CD-ROM - Data Register Read SBPro DESCRIPTION Input port for active CD-ROM drive data and command response reads. PROCEDURE a) Loop until bit 2 = 0 or bit 1 = 0 of CD-ROM Status Port (02x11h read) b) Input byte from CD-ROM Data Register port (02x10h read) SEE ALSO 02x11h CD-ROM - Status Port Read ····················································· 02x13h CD-ROM - Enable Write ····················································· 02x10h CD-ROM - Command Port Write ------------------------------------------------------------------------------ 02x10h CD-ROM - Command Port Write SBPro DESCRIPTION Output port for active CD-ROM drive command sequences. PROCEDURE ??? NOTES ■ Command packets are seven bytes long. ■ Interrupts should be disabled during output. SEE ALSO 02x13h CD-ROM - Enable Write ····················································· 02x10h CD-ROM - Data Register Read ------------------------------------------------------------------------------ 02x11h CD-ROM - Status Port Read SBPro DESCRIPTION Indicates whether or not active CD-ROM drive is waiting for command data, has pending data available, or has prepared a command response. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│[3]│ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Write Status (0 = Busy, v1.0+) │ │ │ │ │ │ └─────── Data Available (0 = Ready) │ │ │ │ │ └─────────── Read Status (0 = Ready) │ │ │ │ └─────────────┬─ Reserved (1) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ SEE ALSO 02x10h CD-ROM - Data Register Read 02x10h CD-ROM - Command Port Write ····················································· 02x13h CD-ROM - Enable Write ------------------------------------------------------------------------------ 02x12h CD-ROM - Reset Write SBPro DESCRIPTION Performs complete reset of active CD-ROM drive. PROCEDURE a) Write 001h b) Wait 82µs??? minimum c) Write 000h NOTES ■ Reset will close open drive doors. SEE ALSO 02x13h CD-ROM - Enable Write ------------------------------------------------------------------------------ 02x13h CD-ROM - Enable Write SBPro DESCRIPTION Selects active CD-ROM drive on multiple drive systems. PROCEDURE ??? SEE ALSO 02x10h CD-ROM - Data Register Read 02x10h CD-ROM - Command Port Write 02x11h CD-ROM - Status Port Read 02x12h CD-ROM - Reset Write ------------------------------------------------------------------------------ 0388h AdLib - Status Port Read SB DESCRIPTION Categorizes left-channel synthesizer generated timer interrupts. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (1) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┘ │ │ └─────────────────────── Timer 2 Status (1 = Expired) │ └─────────────────────────── Timer 1 Status (1 = Expired) └─────────────────────────────── Global Timer Status (1 = Active ) NOTES ■ Global Timer Status will be active if either timer has expired. ■ Counter period of Timer 1 is 80µs, and Timer 2 is 230µs. ■ Synthesizer generated timer interrupts are signalled on IRQ0. ■ Alias for FM Music - Left Status Port (02x00h). SEE ALSO 0388h AdLib - Register Port Write 0389h AdLib - Data Register Write ····················································· 02x00h FM Music - Left Status Port Read ------------------------------------------------------------------------------ 0388h AdLib - Register Port Write SB DESCRIPTION Selects register index into left-channel synthesizer data port (0389h) PROCEDURE a) Write register index (0388h) b) Wait 3.3µs (0.0?µs OPL3) c) Write register data (0389h) d) Wait 23µs (0.28µs OPL3) NOTES ■ Original SoundBlaster Pros were equipped with dual OPL2 synthesizers, connecting this channel to the left speaker exclusively; whereas later models began using OPL3-compatible synthesizers, which send all output to both the left and right speakers unless programmed to do otherwise. ■ Alias for FM Music - Left Register Port (02x00h). SEE ALSO 0388h AdLib - Status Port Read 0389h AdLib - Data Register Write ····················································· 02x00h FM Music - Left Register Port Write ------------------------------------------------------------------------------ 0389h AdLib - Data Register Write SB DESCRIPTION References currently selected left-channel synthesizer index register. PROCEDURE a) Write register index (0388h) b) Wait 3.3µs (0.0?µs OPL3) c) Write register data (0389h) d) Wait 23µs (0.28µs OPL3) NOTES ■ Original SoundBlaster Pros were equipped with dual OPL2 synthesizers, connecting this channel to the left speaker exclusively; whereas later models began using OPL3-compatible synthesizers, which send all output to both the left and right speakers unless programmed to do otherwise. ■ Alias for FM Music - Left Data Register (02x01h). SEE ALSO 0388h AdLib - Status Port Read 0388h AdLib - Register Port Write ····················································· 02x01h FM Music - Left Data Register Write ------------------------------------------------------------------------------ 038Ah Advanced AdLib - Status Port Read SB16 DESCRIPTION Categorizes right-channel synthesizer generated timer interrupts. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (1) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┘ │ │ └─────────────────────── Timer 2 Status (1 = Expired) │ └─────────────────────────── Timer 1 Status (1 = Expired) └─────────────────────────────── Global Timer Status (1 = Active ) NOTES ■ Global Timer Status will be active if either timer has expired. ■ Counter period of Timer 1 is 80µs, and Timer 2 is 230µs. ■ Synthesizer generated timer interrupts are signalled on IRQ0. ■ Alias for FM Music - Right Status Port (02x02h) on SB16 or higher. SEE ALSO 038Ah A. AdLib - Register Port Write 038Bh A. AdLib - Data Register Write ····················································· 02x02h FM Music - Right Status Port Read ------------------------------------------------------------------------------ 038Ah Advanced AdLib - Register Port Write SB16 DESCRIPTION Selects register index into right-channel synthesizer data port (038Bh) PROCEDURE a) Write register index (038Ah) b) Wait 3.3µs (0.0?µs OPL3) c) Write register data (038Bh) d) Wait 23µs (0.28µs OPL3) NOTES ■ Original SoundBlaster Pros were equipped with dual OPL2 synthesizers, connecting this channel to the left speaker exclusively; whereas later models began using OPL3-compatible synthesizers, which send all output to both the left and right speakers unless programmed to do otherwise. ■ Alias for FM Music - Right Register Port (02x02h) on SB16 or higher. SEE ALSO 038Ah A. AdLib - Status Port Read 038Bh A. AdLib - Data Register Write ····················································· 02x02h FM Music - Right Register Port Write ------------------------------------------------------------------------------ 038Bh A. AdLib - Data Register Write SB16 DESCRIPTION References currently selected right-channel synthesizer index register. PROCEDURE a) Write register index (038Ah) b) Wait 3.3µs (0.0?µs OPL3) c) Write register data (038Bh) d) Wait 23µs (0.28µs OPL3) NOTES ■ Original SoundBlaster Pros were equipped with dual OPL2 synthesizers, connecting this channel to the left speaker exclusively; whereas later models began using OPL3-compatible synthesizers, which send all output to both the left and right speakers unless programmed to do otherwise. ■ Alias for FM Music - Right Data Register (02x03h) on SB16 or higher. SEE ALSO 038Ah A. AdLib - Status Port Read 038Ah A. AdLib - Register Port Write ····················································· 02x03h FM Music - Right Data Register Write ------------------------------------------------------------------------------ 03x00h MPU-401 - Data Port Read/Write SB16??? DESCRIPTION Port for MPU-401 data transfer. PROCEDURE (R) a) Loop until bit 6 = 0 of MPU-401 Status Port (03x01h read) b) Input byte from MPU-401 Data Register port (03x00h read/write) PROCEDURE (W) a) Loop until bit 7 = 0 of MPU-401 Status Port (03x01h read) b) Output byte to MPU-401 Data Register port (03x00h read/write) SEE ALSO 03x01h MPU-401 - Status Port Read ····················································· 03x01h MPU-401 - Command Port Write ------------------------------------------------------------------------------ 03x01h MPU-401 - Status Port Read SB16??? DESCRIPTION Indicates whether or not MPU-401 has data pending or is awaiting data. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (?) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┘ │ └─────────────────────────── Data Read Register (0 = Ready) └─────────────────────────────── Data Set Ready (0 = Ready) SEE ALSO 03x00h MPU-401 - Data Port Read/Write ····················································· 03x01h MPU-401 - Command Port Write ------------------------------------------------------------------------------ 03x01h MPU-401 - Command Port Write SB16??? DESCRIPTION Output port for MPU-401 command sequences. PROCEDURE (W) a) Loop until bit 7 = 0 of MPU-401 Status Port (03x01h read) b) Output byte to MPU-401 Command Port (03x01h write) SEE ALSO 03x01h MPU-401 - Status Port Read ····················································· 03x00h MPU-401 - Data Port Read/Write ------------------------------------------------------------------------------ 0201h Joystick Status Port Read/Write SB DESCRIPTION Status port for joystick button and position read. JOYSTICK BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Joystick A: Switch X (1 = Reached) │ │ │ │ │ │ └─────── Joystick A: Switch Y (1 = Reached) │ │ │ │ │ └─────────── Joystick B: Switch X (1 = Reached) │ │ │ │ └─────────────── Joystick B: Switch Y (1 = Reached) │ │ │ └─────────────────── Joystick A: Button 1 (0 = Active ) │ │ └─────────────────────── Joystick A: Button 2 (0 = Active ) │ └─────────────────────────── Joystick B: Button 1 (0 = Active ) └─────────────────────────────── Joystick B: Button 2 (0 = Active ) PROCEDURE a) Output byte to Joystick Status Port (0201h read/write) to reset timer b) Loop until all directional bits charge in Joystick Status Port (0201h read/write), use elapsed time waiting on each bit proportionally ============================================================================== DSP COMMANDS ------------------------------------------------------------------------------ 003h ASP Status SB16ASP 004h DSP Status (Obsolete) SB2.0-Pro2 004h ASP ??? SB16ASP 005h ASP ??? SB16ASP 010h Direct DAC, 8-bit SB 014h DMA DAC, 8-bit SB 016h DMA DAC, 2-bit ADPCM SB 017h DMA DAC, 2-bit ADPCM Reference SB 01Ch Auto-Initialize DMA DAC, 8-bit SB2.0 01Fh Auto-Initialize DMA DAC, 2-bit ADPCM Reference SB2.0 020h Direct ADC, 8-bit SB 024h DMA ADC, 8-bit SB 028h Direct ADC, 8-bit (Burst) SB-Pro2 02Ch Auto-Initialize DMA ADC, 8-bit SB2.0 030h MIDI Read Poll SB 031h MIDI Read Interrupt SB 032h MIDI Read Timestamp Poll SB??? 033h MIDI Read Timestamp Interrupt SB??? 034h MIDI Read Poll + Write Poll (UART) SB2.0 035h MIDI Read Interrupt + Write Poll (UART) SB2.0??? 037h MIDI Read Timestamp Interrupt + Write Poll (UART) SB2.0??? 038h MIDI Write Poll SB 040h Set Time Constant SB 041h Set Sample Rate SB16 045h Continue Auto-Initialize DMA, 8-bit SB16 047h Continue Auto-Initialize DMA, 16-bit SB16 048h Set DMA Block Size SB2.0 074h DMA DAC, 4-bit ADPCM SB 075h DMA DAC, 4-bit ADPCM Reference SB 076h DMA DAC, 2.6-bit ADPCM SB 077h DMA DAC, 2.6-bit ADPCM Reference SB 07Dh Auto-Initialize DMA DAC, 4-bit ADPCM Reference SB2.0 07Fh Auto-Initialize DMA DAC, 2.6-bit ADPCM Reference SB2.0 080h Silence DAC SB 090h Auto-Initialize DMA DAC, 8-bit (High Speed) SB2.0-Pro2 098h Auto-Initialize DMA ADC, 8-bit (High Speed) SB2.0-Pro2 0A0h Disable Stereo Input Mode SBPro Only 0A8h Enable Stereo Input Mode SBPro Only 0Bxh/0Cxh Generic DAC/ADC DMA (16-bit, 8-bit) SB16 0D0h Halt DMA Operation, 8-bit SB 0D1h Enable Speaker SB 0D3h Disable Speaker SB 0D4h Continue DMA Operation, 8-bit SB 0D5h Halt DMA Operation, 16-bit SB16 0D6h Continue DMA Operation, 16-bit SB16 0D8h Speaker Status SB 0D9h Exit Auto-Initialize DMA Operation, 16-bit SB16 0DAh Exit Auto-Initialize DMA Operation, 8-bit SB2.0 0E0h DSP Identification SB2.0 0E1h DSP Version SB 0E3h DSP Copyright SBPro2??? 0E4h Write Test Register SB2.0 0E8h Read Test Register SB2.0 0F0h Sine Generator SB 0F1h DSP Auxiliary Status (Obsolete) SB-Pro2 0F2h IRQ Request, 8-bit SB 0F3h IRQ Request, 16-bit SB16 0FBh DSP Status SB16 0FCh DSP Auxiliary Status SB16 0FDh DSP Command Status SB16 ------------------------------------------------------------------------------ 003h ASP Status SB16ASP COMMAND <-STATUS ??? ------------------------------------------------------------------------------ 004h DSP Status (Obsolete) SB2.0-Pro2 COMMAND <-STATUS DESCRIPTION Retrieves information about pending DSP operations. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Speaker Status (1 = Active) │ │ │ │ │ │ └─────── Stereo ADC Status (1 = Active) │ │ │ │ │ └─────────── Reserved (0) │ │ │ │ └─────────────── Direct ADC 8-bit Burst (1 = Active) │ │ │ └─────────────────── DMA DAC 2-bit ADPCM (1 = Active) │ │ └─────────────────────── DMA DAC 2.6-bit ADPCM (1 = Active) │ └─────────────────────────── DMA DAC 4-bit ADPCM (1 = Active) └─────────────────────────────── DMA DAC 8-bit (1 = Active) NOTES ■ SoundBlaster 2.0 implements only bit 3 and 7. ■ SoundBlaster Pro models do not support bit 7. SEE ALSO 0F1h DSP Auxiliary Status (Obsolete) ····················································· 0FBh DSP Status 0FCh DSP Auxiliary Status 0FDh DSP Command Status ····················································· 0D8h Speaker Status ------------------------------------------------------------------------------ 004h ASP ??? SB16ASP COMMAND->??? ??? ------------------------------------------------------------------------------ 005h ASP ??? SB16ASP COMMAND->DATAHIBYTE->DATALOBYTE ??? ------------------------------------------------------------------------------ 010h Direct DAC, 8-bit SB COMMAND->SAMPLEBYTE DESCRIPTION Outputs single sample. PROCEDURE a) Send Direct DAC, 8-bit command (010h) and sample b) Wait for correct timing NOTES ■ Direct mode maximum sample rate is 23KHz. SEE ALSO 020h Direct ADC, 8-bit ------------------------------------------------------------------------------ 014h DMA DAC, 8-bit SB COMMAND->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Initiates 8-bit DMA transfer. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Enable Speaker command (0D1h) d) Setup DMA controller (mode = 048h + channel) e) Perform DMA DAC, 8-bit command (014h) f) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) g) Perform Disable Speaker command (0D3h) LENGTH = SAMPLES - 1 NOTES ■ Use command 0Cxh to avoid SoundBlaster 16 quantization errors. SEE ALSO 0D0h Halt DMA Operation, 8-bit 0D4h Continue DMA Operation, 8-bit ····················································· 01Ch Auto-Initialize DMA DAC, 8-bit 090h Auto-Initialize DMA DAC, 8-bit (High Speed) 0Cxh Generic DAC/ADC DMA, 8-bit ····················································· 017h DMA DAC, 2-bit ADPCM Reference 075h DMA DAC, 4-bit ADPCM Reference 077h DMA DAC, 2.6-bit ADPCM Reference ····················································· 024h DMA ADC, 8-bit ------------------------------------------------------------------------------ 016h DMA DAC, 2-bit ADPCM SB COMMAND->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Initiates 2-bit ADPCM DMA transfer with accumulated reference byte. This operation uses 8-bit DMA mode. PROCEDURE (after command 017h) a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Enable Speaker command (0D1h) d) Setup DMA controller (mode = 048h + channel) e) Perform DMA DAC, 2-bit ADPCM command (016h) f) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) g) Perform Disable Speaker command (0D3h) LENGTH = (SAMPLES-1 + 3)/4 NOTES ■ Supports up to 11KHz on SoundBlaster 1.x ■ Ensoniq Soundscape does not support ADPCM. SEE ALSO 0D0h Halt DMA Operation, 8-bit 0D4h Continue DMA Operation, 8-bit ····················································· 017h DMA DAC, 2-bit ADPCM Reference ····················································· 074h DMA DAC, 4-bit ADPCM 076h DMA DAC, 2.6-bit ADPCM ------------------------------------------------------------------------------ 017h DMA DAC, 2-bit ADPCM Reference SB COMMAND->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Initiates 2-bit ADPCM DMA transfer with new reference byte. This operation uses 8-bit DMA mode. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Enable Speaker command (0D1h) d) Setup DMA controller (mode = 048h + channel) e) Perform DMA DAC, 2-bit ADPCM Reference command (017h) f) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) g) Perform Disable Speaker command (0D3h) LENGTH = (SAMPLES-1 + 3)/4 + 1 NOTES ■ Supports up to 11KHz on SoundBlaster 1.x ■ Ensoniq Soundscape does not support ADPCM. SEE ALSO 0D0h Halt DMA Operation, 8-bit 0D4h Continue DMA Operation, 8-bit ····················································· 016h DMA DAC, 2-bit ADPCM ····················································· 075h DMA DAC, 4-bit ADPCM Reference 077h DMA DAC, 2.6-bit ADPCM Reference ------------------------------------------------------------------------------ 01Ch Auto-Initialize DMA DAC, 8-bit SB2.0 COMMAND DESCRIPTION Initiates auto-initialize 8-bit DMA transfer. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Set DMA Block Size command (048h) d) Perform Enable Speaker command (0D1h) e) Setup DMA controller (mode = 058h + channel) f) Perform Auto-Initialize DMA DAC, 8-bit command (01Ch) g) IRQ: Prepare next half of buffer (not always in handler) h) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) i) Loop to G until complete j) Perform Disable Speaker command (0D3h) k) Perform Halt DMA Operation, 8-bit command (0D0h - for virtual speaker) l) Perform Exit Auto-Initialize DMA Operation, 8-bit command (0DAh) m) Perform Halt DMA Operation, 8-bit command (0D0h - for virtual speaker) NOTES ■ Supports up to 23KHz (11.5KHz stereo???) ■ Exit auto-initialized mode by programming single-cycle DMA output or with Exit Auto-Initialize DMA Operation, 8-bit (0DAh). ■ Use command 0Cxh to avoid SoundBlaster 16 quantization errors. LENGTH = (SAMPLES + 1)/2 - 1 SEE ALSO 048h Set DMA Block Size ····················································· 0D0h Halt DMA Operation, 8-bit 045h Continue Auto-Initialize DMA Operation, 8-bit 0DAh Exit Auto-Initialize DMA Operation, 8-bit ····················································· 090h Auto-Initialize DMA DAC, 8-bit (High Speed) 0Cxh Generic DAC/ADC DMA, 8-bit ------------------------------------------------------------------------------ 01Fh Auto-Initialize DMA DAC, 2-bit ADPCM Reference SB2.0 COMMAND DESCRIPTION Initiates auto-initialize 2-bit ADPCM DMA transfer with reference byte. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Set DMA Block Size command (048h) d) Perform Enable Speaker command (0D1h) e) Setup DMA controller (mode = 058h + channel) f) Perform Auto-Initialize DMA DAC, 2-bit ADPCM command (01Fh) g) IRQ: Prepare next half of buffer (not always in handler) h) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) i) Loop to G until complete j) Perform Disable Speaker command (0D3h) k) Perform Halt DMA Operation, 8-bit command (0D0h - for virtual speaker) l) Perform Exit Auto-Initialize DMA Operation, 8-bit command (0DAh) m) Perform Halt DMA Operation, 8-bit command (0D0h - for virtual speaker) NOTES ■ Exit auto-initialized mode by programming single-cycle DMA output or with Exit Auto-Initialize DMA Operation, 8-bit (0DAh). ■ Ensoniq Soundscape does not support ADPCM. SAMPLEBYTES = (SAMPLES + 3)/4 + 1 LENGTH = (SAMPLEBYTES + 1)/2 - 1 SEE ALSO 048h Set DMA Block Size ····················································· 0D0h Halt DMA Operation, 8-bit 045h Continue Auto-Initialize DMA Operation, 8-bit 0DAh Exit Auto-Initialize DMA Operation, 8-bit ····················································· 017h DMA DAC, 2-bit ADPCM Reference ····················································· 07Dh Auto-Initialize DMA DAC, 4-bit ADPCM Reference 07Fh Auto-Initialize DMA DAC, 2.6-bit ADPCM Reference ------------------------------------------------------------------------------ 020h Direct ADC, 8-bit SB COMMAND <-SAMPLEBYTE DESCRIPTION Inputs single sample. PROCEDURE a) Send Direct ADC, 8-bit command (020h) b) Read sample c) Wait for correct timing NOTES ■ Direct mode maximum sample rate is 23KHz. SEE ALSO 010h Direct DAC, 8-bit ------------------------------------------------------------------------------ 024h DMA ADC, 8-bit SB COMMAND->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Initiates 8-bit DMA transfer (record). PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Enable Speaker command (0D1h) d) Setup DMA controller (mode = 044h + channel) e) Perform DMA ADC, 8-bit command (024h) f) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) g) Perform Disable Speaker command (0D3h) LENGTH = SAMPLES - 1 NOTES ■ SoundBlasters prior to SB16 return the first sample in direct mode. SEE ALSO 0D0h Halt DMA Operation, 8-bit 0D4h Continue DMA Operation, 8-bit ····················································· 02Ch Auto-Initialize DMA ADC, 8-bit 098h Auto-Initialize DMA ADC, 8-bit (High Speed) 0Cxh Generic DAC/ADC DMA, 8-bit ------------------------------------------------------------------------------ 028h Direct ADC, 8-bit (Burst) SB-Pro2 COMMAND <-SAMPLEBYTE0...SAMPLEBYTEn DESCRIPTION ??? PROCEDURE ??? NOTES ■ Terminate operation with DSP reset. SEE ALSO 020h Direct ADC, 8-bit ------------------------------------------------------------------------------ 02Ch Auto-Initialize DMA ADC, 8-bit SB2.0 COMMAND DESCRIPTION Initiates auto-initialize 8-bit DMA transfer (record). PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Set DMA Block Size command (048h) d) Perform Enable Speaker command (0D1h) e) Setup DMA controller (mode = 054h + channel) f) Perform Auto-Initialize DMA ADC, 8-bit command (02Ch) g) IRQ: Prepare next half of buffer (not always in handler) h) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) i) Loop to G until complete j) Perform Disable Speaker command (0D3h) k) Perform Halt DMA Operation, 8-bit command (0D0h - for virtual speaker) l) Perform Exit Auto-Initialize DMA Operation, 8-bit command (0DAh) m) Perform Halt DMA Operation, 8-bit command (0D0h - for virtual speaker) NOTES ■ Supports up to 23KHz (11.5KHz stereo???) ■ Exit auto-initialized mode by programming single-cycle DMA output or with Exit Auto-Initialize DMA Operation, 8-bit (0DAh). ■ Use command 0Cxh to avoid SoundBlaster 16 quantization errors. LENGTH = (SAMPLES + 1)/2 - 1 SEE ALSO 048h Set DMA Block Size ····················································· 0D0h Halt DMA Operation, 8-bit 045h Continue Auto-Initialize DMA Operation, 8-bit 0DAh Exit Auto-Initialize DMA Operation, 8-bit ····················································· 098h Auto-Initialize DMA ADC, 8-bit (High Speed) 0Cxh Generic DAC/ADC DMA, 8-bit ------------------------------------------------------------------------------ 030h MIDI Read Poll SB COMMAND <-MIDICODE DESCRIPTION Reads MIDI code. PROCEDURE a) Send MIDI Read Poll command (030h) b) Read MIDI code when available NOTES ■ SoundBlasters buffer up to 64bytes of MIDI data. SEE ALSO 031h MIDI Read Interrupt ····················································· 032h MIDI Read Timestamp Poll 033h MIDI Read Timestamp Interrupt ····················································· 034h MIDI Read Poll + Write Poll (UART) 035h MIDI Read Interrupt + Write Poll (UART) 037h MIDI Read Timestamp Interrupt + Write Poll (UART) ····················································· 038h MIDI Write Poll ------------------------------------------------------------------------------ 031h MIDI Read Interrupt SB COMMAND {<-MIDICODE} DESCRIPTION Generates interrupt when MIDI code is available. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform MIDI Read Interrupt command (031h) c) IRQ: Read MIDI code d) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) e) Perform MIDI Read Interrupt command (031h) to terminate NOTES ■ SoundBlasters buffer up to 64bytes of MIDI data. SEE ALSO 033h MIDI Read Timestamp Interrupt ····················································· 035h MIDI Read Interrupt + Write Poll (UART) 037h MIDI Read Timestamp Interrupt + Write Poll (UART) ····················································· 030h MIDI Read Poll ----------------------------------------------------------------------------- 032h MIDI Read Timestamp Poll SB??? COMMAND <-TIMESTAMPLOBYTE<-TIMESTAMPMIDBYTE<-TIMESTAMPHIBYTE<-MIDICODE DESCRIPTION Reads MIDI code with timestamp. PROCEDURE a) Send MIDI Read Timestamp Poll command (032h) b) Read timestamp and MIDI code when available NOTES ■ Timestamp if 24-bit value containing the time since the last MIDI command in milliseconds. ■ SoundBlasters buffer up to 64bytes of MIDI data. SEE ALSO 033h MIDI Read Timestamp Interrupt ····················································· 037h MIDI Read Timestamp Interrupt + Write Poll (UART) ------------------------------------------------------------------------------ 033h MIDI Read Timestamp Interrupt SB??? COMMAND {<-TIMESTAMPLOBYTE<-TIMESTAMPMIDBYTE<-TIMESTAMPHIBYTE<-MIDICODE} DESCRIPTION Generates interrupt when MIDI code is available, includes timestamp. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform MIDI Read Interrupt with Timestamp command (033h) c) IRQ: Read MIDI code with timestamp d) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) e) Perform MIDI Read Interrupt with Timestamp command (033h) to terminate NOTES ■ Timestamp if 24-bit value containing the time since the last MIDI command in milliseconds. ■ SoundBlasters buffer up to 64bytes of MIDI data. SEE ALSO 032h MIDI Read Timestamp Poll ····················································· 037h MIDI Read Timestamp Interrupt + Write Poll (UART) ------------------------------------------------------------------------------ 034h MIDI Read Poll + Write Poll (UART) SB2.0 COMMAND [->MIDICODE] [<-MIDICODE] DESCRIPTION Enables UART mode, where all DSP read/writes are interpreted as MIDI codes. PROCEDURE a) Send MIDI Read Poll + Write Poll (UART) command (034h) b) Send and receive MIDI codes c) Reset DSP to terminate NOTES ■ Disable UART mode with DSP reset (port 02x06h) ■ Read/write status must still be checked (port 02x0Eh/02x0Ch) ■ SoundBlasters buffer up to 64bytes of MIDI data. SEE ALSO 030h MIDI Read Poll 038h MIDI Write Poll ····················································· 035h MIDI Read Interrupt + Write Poll (UART) 037h MIDI Read Timestamp Interrupt + Write Poll (UART) ------------------------------------------------------------------------------ 035h MIDI Read Interrupt + Write Poll (UART) SB2.0??? COMMAND [->MIDICODE] {<-MIDICODE} DESCRIPTION Enables UART mode with interrupt, where all DSP writes are interpreted as MIDI codes and interrupts are generated when a MIDI code is to be read. PROCEDURE a) Send MIDI Read Interrupt + Write Poll (UART) command (035h) b) Send and receive MIDI codes (see command 031h) c) Reset DSP to terminate NOTES ■ Disable UART mode with DSP reset (port 02x06h) ■ Write buffer status must still be checked (port 02x0Ch) ■ SoundBlasters buffer up to 64bytes of MIDI data. SEE ALSO 034h MIDI Read Poll + Write Poll (UART) 037h MIDI Read Timestamp Interrupt + Write Poll (UART) ····················································· 031h MIDI Read Interrupt ------------------------------------------------------------------------------ 037h MIDI Read Timestamp Interrupt + Write Poll (UART) SB2.0??? COMMAND [->MIDICODE] {<-TIMESTAMPLOBYTE<-TIMESTAMPMIDBYTE<-TIMESTAMPHIBYTE<-MIDICODE} DESCRIPTION Enables UART mode with interrupt, where all DSP writes are interpreted as MIDI codes and interrupts are generated when a timestamped MIDI code is to be read. PROCEDURE a) Send MIDI Read Timestamp Interrupt + Write Poll (UART) command (037h) b) Send and receive MIDI codes with timestamps (see command 033h) c) Reset DSP to terminate NOTES ■ Disable UART mode with DSP reset (port 02x06h) ■ Write buffer status must still be checked (port 02x0Ch) ■ SoundBlasters buffer up to 64bytes of MIDI data. SEE ALSO 034h MIDI Read Poll + Write Poll (UART) 035h MIDI Read Interrupt + Write Poll (UART) ····················································· 038h MIDI Write Poll ------------------------------------------------------------------------------ 038h MIDI Write Poll SB COMMAND->MIDICODE DESCRIPTION Writes MIDI code. PROCEDURE a) Send MIDI Write Poll command (038h) and data SEE ALSO 034h MIDI Read Poll + Write Poll (UART) 035h MIDI Read Interrupt + Write Poll (UART) 037h MIDI Read Timestamp Interrupt + Write Poll (UART) ····················································· 030h MIDI Read Poll ------------------------------------------------------------------------------ 040h Set Time Constant SB COMMAND->TIMEBYTE DESCRIPTION Sets sample rate through internal I/O transfer timer. FORMULA TimeConstant = 256 - (1000000 / (SampleChannels * SampleRate)) NOTES ■ For non-SoundBlaster Pro cards, always set SampleChannels equal to one. SEE ALSO 041h Set Sample Rate ------------------------------------------------------------------------------ 041h Set Sample Rate SB16 COMMAND->RATEHIBYTE->RATELOBYTE DESCRIPTION Sets sample rate. NOTES ■ Sampling rate precision is truncated to nearest time constant. ■ Sampling rate is programmed independent of stereo or monaural modes. SEE ALSO 040h Set Time Constant ------------------------------------------------------------------------------ 045h Continue Auto-Initialize DMA, 8-bit SB16 COMMAND DESCRIPTION Continues a halted auto-initialized 8-bit DMA operation. SEE ALSO 0DAh Exit Auto-Initialize DMA Operation, 8-bit ····················································· 0Cxh Generic DAC/ADC, 8-bit ····················································· 01Ch Auto-Initialize DMA DAC, 8-bit 01Fh Auto-Initialize DMA DAC, 2-bit ADPCM 02Ch Auto-Initialize DMA ADC, 8-bit 07Dh Auto-Initialize DMA DAC, 4-bit ADPCM 07Fh Auto-Initialize DMA DAC, 2.6-bit ADPCM 090h Auto-Initialize DMA DAC, 8-bit (High Speed) 098h Auto-Initialize DMA ADC, 8-bit (High Speed) ------------------------------------------------------------------------------ 047h Continue Auto-Initialize DMA, 16-bit SB16 COMMAND DESCRIPTION Continues a halted auto-initialized 16-bit DMA operation. SEE ALSO 0D9h Exit Auto-Initialize DMA, 16-bit ····················································· 0Bxh Generic DAC/ADC, 16-bit ------------------------------------------------------------------------------ 048h Set DMA Block Size SB2.0 COMMAND->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Set DMA transfer size for auto-initialize and high speed modes. SAMPLEBYTES = SAMPLES 8-bit (SAMPLES-1 + 1)/2 + 1 4-bit ADPCM + Reference (SAMPLES-1 + 2)/3 + 1 2.6-bit ADPCM + Reference (SAMPLES-1 + 3)/4 + 1 2-bit ADPCM + Reference LENGTH = SAMPLEBYTES - 1 (Single Cycle) (SAMPLEBYTES + 1)/2 - 1 (Auto-Init ) NOTES ■ Length is always equal to the number of bytes to transfer minus one. SEE ALSO 01Ch Auto-Initialize DMA DAC, 8-bit 01Fh Auto-Initialize DMA DAC, 2-bit ADPCM 02Ch Auto-Initialize DMA ADC, 8-bit 07Dh Auto-Initialize DMA DAC, 4-bit ADPCM 07Fh Auto-Initialize DMA DAC, 2.6-bit ADPCM 090h Auto-Initialize DMA DAC, 8-bit (High Speed) 098h Auto-Initialize DMA ADC, 8-bit (High Speed) ------------------------------------------------------------------------------ 074h DMA DAC, 4-bit ADPCM SB COMMAND->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Initiates 4-bit ADPCM DMA transfer with accumulated reference byte. This operation uses 8-bit DMA mode. PROCEDURE (after command 075h) a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Enable Speaker command (0D1h) d) Setup DMA controller (mode = 048h + channel) e) Perform DMA DAC, 4-bit ADPCM command (074h) f) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) g) Perform Disable Speaker command (0D3h) LENGTH = (SAMPLES-1 + 1)/2 NOTES ■ Supports up to 12KHz on SoundBlaster 1.x ■ Ensoniq Soundscape does not support ADPCM. SEE ALSO 0D0h Halt DMA Operation, 8-bit 0D4h Continue DMA Operation, 8-bit ····················································· 074h DMA DAC, 4-bit ADPCM Reference ····················································· 016h DMA DAC, 2-bit ADPCM 076h DMA DAC, 2.6-bit ADPCM ------------------------------------------------------------------------------ 075h DMA DAC, 4-bit ADPCM Reference SB COMMAND->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Initiates 4-bit ADPCM DMA transfer with new reference byte. This operation uses 8-bit DMA mode. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Enable Speaker command (0D1h) d) Setup DMA controller (mode = 048h + channel) e) Perform DMA DAC, 4-bit ADPCM Reference command (075h) f) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) g) Perform Disable Speaker command (0D3h) LENGTH = (SAMPLES-1 + 1)/2 + 1 NOTES ■ Supports up to 12KHz on SoundBlaster 1.x ■ Ensoniq Soundscape does not support ADPCM. SEE ALSO 0D0h Halt DMA Operation, 8-bit 0D4h Continue DMA Operation, 8-bit ····················································· 075h DMA DAC, 4-bit ADPCM ····················································· 017h DMA DAC, 2-bit ADPCM Reference 077h DMA DAC, 2.6-bit ADPCM Reference ------------------------------------------------------------------------------ 076h DMA DAC, 2.6-bit ADPCM SB COMMAND->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Initiates 2.6-bit ADPCM DMA transfer with accumulated reference byte. This operation uses 8-bit DMA mode. PROCEDURE (after command 077h) a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Enable Speaker command (0D1h) d) Setup DMA controller (mode = 048h + channel) e) Perform DMA DAC, 2.6-bit ADPCM command (076h) f) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) g) Perform Disable Speaker command (0D3h) LENGTH = (SAMPLES-1 + 2)/3 NOTES ■ Supports up to 13KHz on SoundBlaster 1.x ■ Ensoniq Soundscape does not support ADPCM. SEE ALSO 0D0h Halt DMA Operation, 8-bit 0D4h Continue DMA Operation, 8-bit ····················································· 077h DMA DAC, 2.6-bit ADPCM Reference ····················································· 016h DMA DAC, 2-bit ADPCM 074h DMA DAC, 4-bit ADPCM ------------------------------------------------------------------------------ 077h DMA DAC, 2.6-bit ADPCM Reference SB COMMAND->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Initiates 2.6-bit ADPCM DMA transfer with new reference byte. This operation uses 8-bit DMA mode. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Enable Speaker command (0D1h) d) Setup DMA controller (mode = 048h + channel) e) Perform DMA DAC, 2.6-bit ADPCM Reference command (077h) f) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) g) Perform Disable Speaker command (0D3h) LENGTH = (SAMPLES-1 + 2)/3 + 1 NOTES ■ Supports up to 13KHz on SoundBlaster 1.x ■ Ensoniq Soundscape does not support ADPCM. SEE ALSO 0D0h Halt DMA Operation, 8-bit 0D4h Continue DMA Operation, 8-bit ····················································· 076h DMA DAC, 2.6-bit ADPCM ····················································· 017h DMA DAC, 2-bit ADPCM Reference 075h DMA DAC, 4-bit ADPCM Reference ------------------------------------------------------------------------------ 07Dh Auto-Initialize DMA DAC, 4-bit ADPCM Reference SB2.0 COMMAND DESCRIPTION Initiates auto-initialize 4-bit ADPCM DMA transfer with reference byte. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Set DMA Block Size command (048h) d) Perform Enable Speaker command (0D1h) e) Setup DMA controller (mode = 058h + channel) f) Perform Auto-Initialize DMA DAC, 4-bit ADPCM command (07Dh) g) IRQ: Prepare next half of buffer (not always in handler) h) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) i) Loop to G until complete j) Perform Disable Speaker command (0D3h) k) Perform Halt DMA Operation, 8-bit command (0D0h - for virtual speaker) l) Perform Exit Auto-Initialize DMA Operation, 8-bit command (0DAh) m) Perform Halt DMA Operation, 8-bit command (0D0h - for virtual speaker) NOTES ■ Exit auto-initialized mode by programming single-cycle DMA output or with Exit Auto-Initialize DMA Operation, 8-bit (0DAh). ■ Ensoniq Soundscape does not support ADPCM. SAMPLEBYTES = (SAMPLES + 1)/2 + 1 LENGTH = (SAMPLEBYTES + 1)/2 - 1 SEE ALSO 048h Set DMA Block Size ····················································· 0D0h Halt DMA Operation, 8-bit 045h Continue Auto-Initialize DMA Operation, 8-bit 0DAh Exit Auto-Initialize DMA Operation, 8-bit ····················································· 075h DMA DAC, 4-bit ADPCM Reference ····················································· 01Fh Auto-Initialize DMA DAC, 2-bit ADPCM Reference 07Fh Auto-Initialize DMA DAC, 2.6-bit ADPCM Reference ------------------------------------------------------------------------------ 07Fh Auto-Initialize DMA DAC, 2.6-bit ADPCM Reference SB2.0 COMMAND DESCRIPTION Initiates auto-initialize 2.6-bit ADPCM DMA transfer with reference byte. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Set DMA Block Size command (048h) d) Perform Enable Speaker command (0D1h) e) Setup DMA controller (mode = 058h + channel) f) Perform Auto-Initialize DMA DAC, 2.6-bit ADPCM command (07Fh) g) IRQ: Prepare next half of buffer (not always in handler) h) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) i) Loop to G until complete j) Perform Disable Speaker command (0D3h) k) Perform Halt DMA Operation, 8-bit command (0D0h - for virtual speaker) l) Perform Exit Auto-Initialize DMA Operation, 8-bit command (0DAh) m) Perform Halt DMA Operation, 8-bit command (0D0h - for virtual speaker) NOTES ■ Exit auto-initialized mode by programming single-cycle DMA output or with Exit Auto-Initialize DMA Operation, 8-bit (0DAh). ■ Ensoniq Soundscape does not support ADPCM. SAMPLEBYTES = (SAMPLES + 2)/3 + 1 LENGTH = (SAMPLEBYTES + 1)/2 - 1 SEE ALSO 048h Set DMA Block Size ····················································· 0D0h Halt DMA Operation, 8-bit 045h Continue Auto-Initialize DMA Operation, 8-bit 0DAh Exit Auto-Initialize DMA Operation, 8-bit ····················································· 077h DMA DAC, 2.6-bit ADPCM Reference ····················································· 01Fh Auto-Initialize DMA DAC, 2-bit ADPCM Reference 07Dh Auto-Initialize DMA DAC, 4-bit ADPCM Reference ------------------------------------------------------------------------------ 080h Silence DAC SB COMMAND->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Outputs block of silent samples at current sample rate, and signals IRQ when complete. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Silence DAC command (080h) d) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) e) Remove IRQ handler (restore vector, restore PIC mask) LENGTH = SAMPLES - 1 SEE ALSO 040h Set Time Constant ------------------------------------------------------------------------------ 090h Auto-Initialize DMA DAC, 8-bit (High Speed) SB2.0-Pro2 COMMAND DESCRIPTION Initiates 8-bit DMA transfer (>23KHz). PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Set DMA Block Size command (048h) d) Perform Enable Speaker command (0D1h) e) Setup DMA controller (mode = 058h + channel) f) Perform Auto-Initialize DMA DAC, 8-bit (HighSpeed) command (090h) g) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) h) Reset DSP (or terminate normally on SB16+) NOTES ■ High speed mode ignores DSP commands during transfers (<SB16). ■ Use command 0Cxh to avoid SoundBlaster 16 quantization errors. SEE ALSO 048h Set DMA Block Size ····················································· 0D0h Halt DMA Operation, 8-bit 045h Continue Auto-Initialize DMA Operation, 8-bit 0DAh Exit Auto-Initialize DMA Operation, 8-bit ····················································· 01Ch Auto-Initialize DMA DAC, 8-bit 0Cxh Generic DAC/ADC DMA, 8-bit ------------------------------------------------------------------------------ 098h Auto-Initialize DMA ADC, 8-bit (High Speed) SB2.0-Pro2 COMMAND DESCRIPTION Initiates 8-bit DMA transfer (record, >23KHz). PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Perform Set DMA Block Size command (048h) d) Perform Enable Speaker command (0D1h) e) Setup DMA controller (mode = 054h + channel) f) Perform Auto-Initialize DMA ADC, 8-bit (HighSpeed) command (098h) g) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) h) Reset DSP (or terminate normally on SB16+) NOTES ■ High speed mode ignores DSP commands during transfers (<SB16). SEE ALSO 048h Set DMA Block Size ····················································· 0D0h Halt DMA Operation, 8-bit 045h Continue Auto-Initialize DMA Operation, 8-bit 0DAh Exit Auto-Initialize DMA Operation, 8-bit ····················································· 02Ch Auto-Initialize DMA ADC, 8-bit 0Cxh Generic DAC/ADC DMA, 8-bit ------------------------------------------------------------------------------ 0A0h Disable Stereo Input Mode SBPro Only COMMAND DESCRIPTION Selects monaural input mode on SoundBlaster Pro. NOTES ■ Monaural input mode is default. ■ SoundBlaster 16 uses command 0Bxh/0Cxh for stereo input. SEE ALSO 0A8h Enable Stereo Input Mode ····················································· 0F1h DSP Auxiliary Status (Obsolete) ------------------------------------------------------------------------------ 0A8h Enable Stereo Input Mode SBPro Only COMMAND DESCRIPTION Selects stereo input mode on SoundBlaster Pro. NOTES ■ Monaural input mode is default. ■ SoundBlaster 16 uses command 0Bxh/0Cxh for stereo input. ■ BUG: Stereo input mode results in playback static. SEE ALSO 0A0h Disable Stereo Input Mode ····················································· 0F1h DSP Auxiliary Status (Obsolete) ------------------------------------------------------------------------------ 0Bxh/0Cxh Generic DAC/ADC DMA (16-bit, 8-bit) SB16 COMMAND->MODE->LENGTHLOBYTE->LENGTHHIBYTE DESCRIPTION Generalized sampling and playback command (includes 16-bit operations). PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform Set Time Constant command (040h), or otherwise set sample rate c) Setup DMA controller (mode = mode + channel) d) Perform Generic DAC/ADC DMA command (0Bxh/0Cxh) e) IRQ: Acknowledge IRQ (input from IRQ Acknowledge port - 02x0Eh/02x0Fh; perform Generic EOI (020h) to appropriate PICs) f) Terminate transfer, method dependent on mode COMMAND BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║(7)│(6)│(5)│(4)│ 3 │ 2 │ 1 │[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Reserved (0) │ │ │ │ │ │ └─────── FIFO Mode (0 = Disable, 1 = Enable) │ │ │ │ │ └─────────── DMA Mode (0 = Single, 1 = Auto-Init) │ │ │ │ └─────────────── Transfer Mode (0 = DAC, 1 = ADC) │ │ │ └─────────────────┐ │ │ └─────────────────────┼─ Sampling Resolution │ └─────────────────────────┤ 1011b = 16-bit, 1100b = 8-bit └─────────────────────────────┘ MODE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│ 5 │ 4 │[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────── Sample Mode (0 = Unsigned, 1 = Signed) │ │ └─────────────────────── Stereo Mode (0 = Monaural, 1 = Stereo) │ └─────────────────────────┬─ Reserved (0) └─────────────────────────────┘ LENGTH = SAMPLES - 1 (even for 16-bit samples) NOTES ■ Enable FIFO mode for high speed mode or large data transfers. ■ BUG: SoundBlaster 16 ADC only accurate to 12-bits. SEE ALSO 0D0h Halt DMA Operation, 8-bit 0D4h Continue DMA Operation, 8-bit 045h Continue Auto-Initialize DMA Operation, 8-bit 0DAh Exit Auto-Initialize DMA Operation, 8-bit ····················································· 0D5h Halt DMA Operation, 16-bit 0D6h Continue DMA Operation, 16-bit 047h Continue Auto-Initialize DMA, 16-bit 0D9h Exit Auto-Initialize DMA Operation, 16-bit ····················································· 014h DMA DAC, 8-bit 024h DMA ADC, 8-bit ····················································· 01Ch Auto-Initialize DMA DAC, 8-bit 02Ch Auto-Initialize DMA ADC, 8-bit ····················································· 090h Auto-Initialize DMA DAC, 8-bit (High Speed) 098h Auto-Initialize DMA ADC, 8-bit (High Speed) ------------------------------------------------------------------------------ 0D0h Halt DMA Operation, 8-bit SB COMMAND DESCRIPTION Pauses 8-bit single-cycle DMA operation. NOTES ■ Halts every 8-bit DMA mode on SoundBlaster 16. ■ BUG: Halts 16-bit DMA operation on early SoundBlaster 16s (4.04). SEE ALSO 0D4h Continue DMA Operation, 8-bit 0DAh Exit Auto-Initialize DMA Operation, 8-bit ------------------------------------------------------------------------------ 0D1h Enable Speaker SB COMMAND DESCRIPTION Enables speaker output. NOTES ■ Reset of DSP disables speaker. ■ BUG: Halts pending DMA operations on SoundBlaster 1.x. ■ BUG: Enabled speaker generates sampling noise on SoundBlaster 2.0. ■ BUG: Speaker MUST be disabled before sampling on SoundBlaster Pro. ■ BUG: Speaker state does NOT physically change on SoundBlaster 16. ■ Originator of noisy 'pops' on some models (capacitor discharge). SEE ALSO 0D3h Disable Speaker ------------------------------------------------------------------------------ 0D3h Disable Speaker SB COMMAND DESCRIPTION Disables speaker output. NOTES ■ Reset of DSP disables speaker. ■ BUG: Halts pending DMA operations on SoundBlaster 1.x. ■ BUG: Enabled speaker generates sampling noise on SoundBlaster 2.0. ■ BUG: Speaker MUST be disabled before sampling on SoundBlaster Pro. ■ BUG: Speaker state does NOT physically change on SoundBlaster 16. ■ Originator of noisy 'pops' on some models (capacitor discharge). SEE ALSO 0D1h Enable Speaker ------------------------------------------------------------------------------ 0D4h Continue DMA Operation, 8-bit SB COMMAND DESCRIPTION Continues a halted 8-bit single-cycle DMA operation. NOTES ■ Continues every 8-bit DMA mode on SoundBlaster 16. ■ BUG: Continues 16-bit DMA operation on early SoundBlaster 16 (4.04). SEE ALSO 0D0h Halt DMA Operation, 8-bit 0DAh Exit Auto-Initialize DMA Operation, 8-bit ------------------------------------------------------------------------------ 0D5h Halt DMA Operation, 16-bit SB16 COMMAND DESCRIPTION Pauses any 16-bit DMA operation. SEE ALSO 0D6h Continue DMA Operation, 16-bit 0D9h Exit Auto-Initialize DMA Operation, 16-bit ------------------------------------------------------------------------------ 0D6h Continue DMA Operation, 16-bit SB16 COMMAND DESCRIPTION Continues any halted 16-bit DMA operation. SEE ALSO 0D5h Halt DMA Operation, 16-bit 0D9h Exit Auto-Initialize DMA Operation, 16-bit ------------------------------------------------------------------------------ 0D8h Speaker Status SB COMMAND <-STATUS DESCRIPTION Determines current status of speaker. STATUS BYTE 000h = Disabled 0FFh = Enabled NOTES ■ Reset of DSP disables speaker. SEE ALSO 0D1h Enable Speaker 0D3h Disable Speaker ····················································· 004h DSP Status (Obsolete) 0F1h DSP Auxiliary Status (Obsolete) ····················································· 0FBh DSP Status 0FCh DSP Auxiliary Status 0FDh DSP Command Status ------------------------------------------------------------------------------ 0D9h Exit Auto-Initialize DMA Operation, 16-bit SB16 COMMAND DESCRIPTION Terminates auto-initialized 16-bit DMA operation after current block. PROCEDURE a) Perform Disable Speaker command (0D3h) b) Perform Halt DMA Operation, 16-bit command (0D5h - virtual speaker) c) Perform Exit Auto-Initialize DMA Operation, 16-bit command (0D9h) d) Perform Halt DMA Operation, 16-bit command (0D5h - virtual speaker) NOTES ■ Halt commands are required for immediate termination and to quiet SB16. SEE ALSO 0D5h Halt DMA Operation, 16-bit 047h Continue Auto-Initialize DMA, 16-bit ····················································· 0D3h Disable Speaker ------------------------------------------------------------------------------ 0DAh Exit Auto-Initialize DMA Operation, 8-bit SB2.0 COMMAND DESCRIPTION Terminates auto-initialized 8-bit DMA operations after current block. PROCEDURE a) Perform Disable Speaker command (0D3h) b) Perform Halt DMA Operation, 8-bit command (0D0h - virtual speaker) c) Perform Exit Auto-Initialize DMA Operation, 8-bit command (0DAh) d) Perform Halt DMA Operation, 8-bit command (0D0h - virtual speaker) NOTES ■ Halt commands are required for immediate termination and to quiet SB16. SEE ALSO 0D0h Halt DMA Operation, 8-bit 045h Continue Auto-Initialize DMA, 8-bit ····················································· 0D3h Disable Speaker ------------------------------------------------------------------------------ 0E0h DSP Identification SB2.0 COMMAND->DATA <-NOT(DATA) DESCRIPTION Returns bitwise NOT of data byte. NOTES ■ Results reliable only after DSP reset on early models. SEE ALSO 0E1h DSP Version 0E3h DSP Copyright ------------------------------------------------------------------------------ 0E1h DSP Version SB COMMAND <-MAJORVERSIONBYTE<-MINORVERSIONBYTE DESCRIPTION Determines DSP major and minor version. MODEL VERSION SoundBlaster 1.0 1.?? (1.05???) SoundBlaster 1.5 1.?? (1.05???) SoundBlaster 2.0 2.xx (2.01) SoundBlaster Pro 3.00 (???) SoundBlaster Pro 2 3.01+ (3.01, 3.02) SoundBlaster 16 4.0x (4.04, 4.05) SoundBlaster 16 SCSI-2 4.11 (4.11) SoundBlaster AWE32 4.12+ (4.12) NOTES ■ Ensure that no other card is mapped at the same port address by performing this command twice, checking for a consistent result. ■ BUG: Some SB1.x clones errantly return version 2.00. ■ BUG: Some SB16 SCSI-2s experience daughterboard communication errors. SEE ALSO 0E0h DSP Identification 0E3h DSP Copyright ------------------------------------------------------------------------------ 0E3h DSP Copyright SBPro2??? COMMAND <-ASCII0...ASCIIn<-000h DESCRIPTION Reads DSP copyright string. PROCEDURE a) Send DSP Copyright command byte (0E3h) b) Read string byte c) Loop to B while string byte is not zero SEE ALSO 0E0h DSP Identification 0E1h DSP Version ------------------------------------------------------------------------------ 0E4h Write Test Register SB2.0 COMMAND->TESTBYTE DESCRIPTION Writes diagnostic register. NOTES ■ DSP reset does not clear the test register. SEE ALSO 0E8h Read Test Register ------------------------------------------------------------------------------ 0E8h Read Test Register SB2.0 COMMAND <-TESTBYTE DESCRIPTION Reads diagnostic register. NOTES ■ DSP reset does not clear the test register. SEE ALSO 0E4h Write Test Register ------------------------------------------------------------------------------ 0F0h Sine Generator SB COMMAND DESCRIPTION Diagnostic peak-to-peak sine wave generator. NOTES ■ Disable sound with DSP reset. ■ Sinusodal frequency is about 2KHz. ■ Sets time constant to approximately 0C0h (15625Hz). ■ Enables speaker on models prior to SoundBlaster 16. ------------------------------------------------------------------------------ 0F1h DSP Auxiliary Status (Obsolete) SB-Pro2 COMMAND <-STATUS DESCRIPTION Retrieves auxiliary information about pending DSP operations. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │[1]│ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Speaker Status (0 = Enabled) │ │ │ │ │ │ └─────── Reserved (1) │ │ │ │ │ └─────────── DSPC 0ACh ??? │ │ │ │ └─────────────── Stereo Input Mode (1 = Stereo) │ │ │ └─────────────────── Reserved (1) │ │ └─────────────────────── DSPC 020h-02Fh (SB1.x) ??? │ └─────────────────────────── DSPC 02Dh-02Fh (SB1.x) ??? └─────────────────────────────── ??? NOTES ■ SoundBlaster Pro introduces bit 3. SEE ALSO 004h DSP Status (Obsolete) ····················································· 0FBh DSP Status 0FCh DSP Auxiliary Status 0FDh DSP Command Status ····················································· 0D8h Speaker Status ------------------------------------------------------------------------------ 0F2h IRQ Request, 8-bit SB COMMAND DESCRIPTION Triggers 8-bit interrupt. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform IRQ Request, 8-bit command (0F2h) c) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 8-bit port - 02x0Eh; perform Generic EOI (020h) to appropriate PICs) SEE ALSO 0F3h Interrupt Request, 16-bit ------------------------------------------------------------------------------ 0F3h IRQ Request, 16-bit SB16 COMMAND DESCRIPTION Triggers 16-bit interrupt. PROCEDURE a) Install IRQ handler (hook vector, update PIC mask) b) Perform IRQ Request, 16-bit command (0F3h) c) IRQ: Acknowledge IRQ (input from IRQ Acknowledge, 16-bit port - 02x0Fh; perform Generic EOI (020h) to appropriate PICs) SEE ALSO 0F2h Interrupt Request, 8-bit ------------------------------------------------------------------------------ 0FBh DSP Status SB16 COMMAND <-STATUS DESCRIPTION Retrieves information about pending DSP operations. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── DMA DAC, 8-bit (1 = Active) │ │ │ │ │ │ └─────── DMA ADC, 8-bit (1 = Active) │ │ │ │ │ └─────────── DMA DAC, 16-bit (1 = Active) │ │ │ │ └─────────────── DMA ADC, 16-bit (1 = Active) │ │ │ └─────────────────── Virtual Speaker (1 = Active) │ │ └─────────────────────── ??? │ └─────────────────────────── DSPC 04Fh ??? └─────────────────────────────── Time Constant (1 = Modified) NOTES ■ Time Constant bit will not be set if too large a time constant was programmed (low sample rate). ■ MediaVision 3D-series cards use this command for DMA and IRQ selection. SEE ALSO 0FCh DSP Auxiliary Status 0FDh DSP Command Status ····················································· 004h DSP Status (Obsolete) 0F1h DSP Auxiliary Status (Obsolete) ····················································· 0D8h Speaker Status ------------------------------------------------------------------------------ 0FCh DSP Auxiliary Status SB16 COMMAND <-STATUS DESCRIPTION Retrieves auxiliary information about pending DMA operations. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── ??? │ │ │ │ │ │ └─────── DAC/ADC DMA (1 = Synchronous) │ │ │ │ │ └─────────── Auto-Init DMA, 8-bit (1 = Active) │ │ │ │ └─────────────── ??? │ │ │ └─────────────────── Auto-Init DMA, 16-bit (1 = Active) │ │ └─────────────────────── ??? │ └─────────────────────────── ??? └─────────────────────────────── ??? SEE ALSO 0FBh DSP Status 0FDh DSP Command Status ····················································· 004h DSP Status (Obsolete) 0F1h DSP Auxiliary Status (Obsolete) ····················································· 0D8h Speaker Status ------------------------------------------------------------------------------ 0FDh DSP Command Status SB16 COMMAND <-COMMANDSTATUS DESCRIPTION Retrieves most recently successful DSP command. NOTES ■ Reseting the DSP clears this variable. ■ Command does not support all valid DSP commands, but most. ■ MediaVision 3D-series cards use this command for DMA and IRQ detection. SEE ALSO 0FBh DSP Status 0FCh DSP Auxiliary Status ····················································· 004h DSP Status (Obsolete) 0F1h DSP Auxiliary Status (Obsolete) ····················································· 0D8h Speaker Status ============================================================================== MIXER REGISTERS ------------------------------------------------------------------------------ 000h Reset Write SBPro 001h Status Read SBPro 002h Master Volume Read/Write SBPro Only 004h DAC Level Read/Write SBPro 006h FM Output Control Read/Write SBPro Only 00Ah Microphone Level Read/Write SBPro 00Ch Input/Filter Select Read/Write SBPro Only 00Eh Output/Stereo Select Read/Write SBPro Only 022h Master Volume Read/Write SBPro 026h FM Level Read/Write SBPro 028h CD Audio Level Read/Write SBPro 02Eh Line In Level Read/Write SBPro 030h Master Volume Left Read/Write SB16 031h Master Volume Right Read/Write SB16 032h DAC Level Left Read/Write SB16 033h DAC Level Right Read/Write SB16 034h FM Level Left Read/Write SB16 035h FM Level Right Read/Write SB16 036h CD Audio Level Left Read/Write SB16 037h CD Audio Level Right Read/Write SB16 038h Line In Level Left Read/Write SB16 039h Line In Level Right Read/Write SB16 03Ah Microphone Level Read/Write SB16 03Bh PC Speaker Level Read/Write SB16 03Ch Output Control Read/Write SB16 03Dh Input Control Left Read/Write SB16 03Eh Input Control Right Read/Write SB16 03Fh Input Gain Control Left Read/Write SB16 040h Input Gain Control Right Read/Write SB16 041h Output Gain Control Left Read/Write SB16 042h Output Gain Control Right Read/Write SB16 043h Automatic Gain Control (AGC) Read/Write SB16 044h Treble Left Read/Write SB16 045h Treble Right Read/Write SB16 046h Bass Left Read/Write SB16 047h Bass Right Read/Write SB16 080h IRQ Select Read/Write SB16 081h DMA Select Read/Write SB16 082h IRQ Status Read SB16 ------------------------------------------------------------------------------ 000h Reset Write SBPro DESCRIPTION Resets mixer to default settings. PROCEDURE a) Load index register b) Wait 100µs c) Write reset stop RESET BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Reset Stop (0) │ │ │ │ │ │ └─────┬─ Reserved (0) │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Defaults documented for each register (SBPro, SB16) ------------------------------------------------------------------------------ 001h Status Read SBPro DESCRIPTION Contains previously selected register value. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Mixer Data Register value │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ SoundBlaster 16 sets bit 7 if previous mixer index invalid. ■ Status bytes initially 080h on startup for all but level bytes (SB16) ------------------------------------------------------------------------------ 002h Master Volume Read/Write SBPro Only VOLUME BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │[4]│ 3 │ 2 │ 1 │[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Reserved (1) │ │ │ │ │ │ └─────┬─ Right Master Volume bit 3-1 (SBPro) │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────── Reserved (1) │ │ └─────────────────────┬─ Left Master Volume bit 3-1 (SBPro) │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT 099h, N/A NOTES ■ Same as register 022h selection. SEE ALSO 022h Master Volume Read/Write ····················································· 030h Master Volume Left Read/Write 031h Master Volume Right Read/Write ------------------------------------------------------------------------------ 004h DAC Level Read/Write SBPro LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Right DAC Level bit 0 (SB16, SBPro=1) │ │ │ │ │ │ └─────┬─ Right DAC Level bit 3-1 (SBPro) │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────── Left DAC Level bit 0 (SB16, SBPro=1) │ │ └─────────────────────┬─ Left DAC Level bit 3-1 (SBPro) │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT 099h, 0CCh NOTES ■ Mixer detection can be accomplished by looking for this register index. ■ SoundBlaster 16 will automatically update registers 031h and 032h, transferring bits 7-4 and setting bit 3. SEE ALSO 032h DAC Level Left Read/Write 033h DAC Level Right Read/Write ------------------------------------------------------------------------------ 006h FM Output Control Read/Write SBPro Only CONTROL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│ 6 │ 5 │[4]│ 3 │ 2 │ 1 │[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Reserved (1) │ │ │ │ │ │ └─────┬─ FM Level (bits 3-1, see notes) │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────── Reserved (1) │ │ └─────────────────────── FM Left Channel (0 = On, 1 = Off) │ └─────────────────────────── FM Right Channel (0 = On, 1 = Off) └─────────────────────────────── Reserved (0) DEFAULT 019h, N/A NOTES ■ FM level controls both channels. ■ If only one channel is active, the inactive channel's voices will be routed through the active one. ■ SoundBlaster Pro will automatically update register 026h, transferring source bits 3-0 to destination bits 7-4 and 3-0. SEE ALSO 026h FM Level Read/Write ····················································· 034h FM Level Left Read/Write 035h FM Level Right Read/Write ------------------------------------------------------------------------------ 00Ah Microphone Level Read/Write SBPro LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│[3]│ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Microphone Level bit 0 (SB16, SBPro=0) │ │ │ │ │ │ └─────┬─ Microphone Level bit 2-1 (SBPro) │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Reserved (0) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT 011h, 000h SEE ALSO 03Ah Microphone Level Read/Write ------------------------------------------------------------------------------ 00Ch Input/Filter Select Read/Write SBPro Only SELECT BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│ 5 │[4]│ 3 │ 2 │ 1 │[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Reserved (1) │ │ │ │ │ │ └─────┬─ Input Select (0 = Microphone, │ │ │ │ │ └─────────┘ 1 = CD Audio, 3 = Line In) │ │ │ │ └─────────────── Frequency (0 = Highpass, 1 = Lowpass) │ │ │ └─────────────────── Reserved (0) │ │ └─────────────────────── Filter Input (0 = On, 1 = Off) │ └─────────────────────────┬─ Reserved (0) └─────────────────────────────┘ DEFAULT 011h, N/A SEE ALSO 03Dh Input Control Left Read/Write 03Eh Input Control Right Read/Write ------------------------------------------------------------------------------ 00Eh Output/Stereo Select Read/Write SBPro Only SELECT BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│ 5 │[4]│[3]│[2]│ 1 │[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Reserved (1) │ │ │ │ │ │ └─────── Stereo Output Mode (1 = Stereo) │ │ │ │ │ └─────────┬─ Reserved (0) │ │ │ │ └─────────────┘ │ │ │ └─────────────────── Reserved (1) │ │ └─────────────────────── Filter Output (0 = On, 1 = Off) │ └─────────────────────────┬─ Reserved (0) └─────────────────────────────┘ DEFAULT 011h, N/A NOTES ■ SoundBlaster 16 uses command 0Bxh/0Cxh for stereo output. SEE ALSO 03Ch Output Control Read/Write ------------------------------------------------------------------------------ 022h Master Volume Read/Write SBPro VOLUME BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Right Master bit 0 (SB16, SBPro=1) │ │ │ │ │ │ └─────┬─ Right Master bit 3-1 (SBPro) │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────── Left Master bit 0 (SB16, SBPro=1) │ │ └─────────────────────┬─ Left Master bit 3-1 (SBPro) │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT 011h, 0CCh NOTES ■ SoundBlaster 16 will automatically update registers 030h and 031h, transferring bits 7-4 and setting bit 3. ■ SoundBlaster Pro register 002h is the same as this. SEE ALSO 002h Master Volume Read/Write ····················································· 030h Master Volume Left Read/Write 031h Master Volume Right Read/Write ------------------------------------------------------------------------------ 026h FM Level Read/Write SBPro LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Right FM Level bit 0 (SB16, SBPro=1) │ │ │ │ │ │ └─────┬─ Right FM Level bit 3-1 (SBPro) │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────── Left FM Level bit 0 (SB16, SBPro=1) │ │ └─────────────────────┬─ Left FM Level bit 3-1 (SBPro) │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT 011h, 0CCh NOTES ■ SoundBlaster 16 will automatically update registers 033h and 034h, transferring bits 7-4 and setting bit 3. ■ SoundBlaster Pro will automatically update register 006h, transferring bits 3-1 and setting bit 0. SEE ALSO 006h FM Output Control Read/Write ····················································· 034h FM Level Left Read/Write 035h FM Level Right Read/Write ------------------------------------------------------------------------------ 028h CD Audio Level Read/Write SBPro LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Right CD Audio bit 0 (SB16, SBPro=1) │ │ │ │ │ │ └─────┬─ Right CD Audio bit 3-1 (SBPro) │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────── Left CD Audio bit 0 (SB16, SBPro=1) │ │ └─────────────────────┬─ Left CD Audio bit 3-1 (SBPro) │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT 011h, 000h NOTES ■ SoundBlaster 16 will automatically update registers 035h and 036h, transferring bits 7-4 and setting bit 3. SEE ALSO 036h CD Audio Level Left Read/Write 037h CD Audio Level Right Read/Write ------------------------------------------------------------------------------ 02Eh Line In Level Read/Write SBPro LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Right Line In bit 0 (SB16, SBPro=1) │ │ │ │ │ │ └─────┬─ Right Line In bit 3-1 (SBPro) │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────── Left Line In bit 0 (SB16, SBPro=1) │ │ └─────────────────────┬─ Left Line In bit 3-1 (SBPro) │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT 011h, 000h NOTES ■ SoundBlaster 16 will automatically update registers 037h and 038h, transferring bits 7-4 and setting bit 3. SEE ALSO 038h Line In Level Left Read/Write 039h Line In Level Right Read/Write ------------------------------------------------------------------------------ 030h Master Volume Left Read/Write SB16 VOLUME BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Left Master Volume (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 0C0h NOTES ■ SoundBlaster 16 will automatically transfer bits 7-4 to bits 7-4 of register 022h ■ SoundBlaster Pro selects register 020h for 030h. SEE ALSO 031h Master Volume Right Read/Write ····················································· 022h Master Volume Read/Write ------------------------------------------------------------------------------ 031h Master Volume Right Read/Write SB16 VOLUME BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Right Master Volume (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 0C0h NOTES ■ SoundBlaster 16 will automatically transfer bits 7-4 to bits 3-0 of register 022h. SEE ALSO 030h Master Volume Left Read/Write ····················································· 022h Master Volume Read/Write ------------------------------------------------------------------------------ 032h DAC Level Left Read/Write SB16 LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Left DAC Level (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 0C0h NOTES ■ SoundBlaster 16 will automatically transfer bits 7-4 to bits 7-4 of register 024h. ■ SoundBlaster Pro selects register 022h for 032h. SEE ALSO 033h DAC Level Right Read/Write ····················································· 004h DAC Level Read/Write ------------------------------------------------------------------------------ 033h DAC Level Right Read/Write SB16 LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Right DAC Level (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 0C0h NOTES ■ SoundBlaster 16 will automatically transfer bits 7-4 to bits 3-0 of register 024h. SEE ALSO 032h DAC Level Left Read/Write ····················································· 004h DAC Level Read/Write ------------------------------------------------------------------------------ 034h FM Level Left Read/Write SB16 LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Left FM Level (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 0C0h NOTES ■ SoundBlaster 16 will automatically transfer bits 7-4 to bits 7-4 of register 026h. SEE ALSO 035h FM Level Right Read/Write ····················································· 006h FM Output Control Read/Write 026h FM Level Read/Write ------------------------------------------------------------------------------ 035h FM Level Right Read/Write SB16 LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Right FM Level (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 0C0h NOTES ■ SoundBlaster 16 will automatically transfer bits 7-4 to bits 3-0 of register 026h. SEE ALSO 034h FM Level Left Read/Write ····················································· 006h FM Output Control Read/Write 026h FM Level Read/Write ------------------------------------------------------------------------------ 036h CD Audio Level Left Read/Write SB16 LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Left CD Audio Level (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 000h NOTES ■ SoundBlaster 16 will automatically transfer bits 7-4 to bits 7-4 of register 028h. ■ SoundBlaster Pro selects register 026h for 036h. SEE ALSO 037h CD Audio Level Right Read/Write ····················································· 028h CD Audio Level Read/Write ------------------------------------------------------------------------------ 037h CD Audio Level Right Read/Write SB16 LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Right CD Audio Level (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 000h NOTES ■ SoundBlaster 16 will automatically transfer bits 7-4 to bits 3-0 of register 028h. SEE ALSO 036h CD Audio Level Left Read/Write ····················································· 028h CD Audio Level Read/Write ------------------------------------------------------------------------------ 038h Line In Level Left Read/Write SB16 LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Left Line In Level (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 000h NOTES ■ SoundBlaster 16 will automatically transfer bits 7-4 to bits 7-4 of register 02Eh. ■ SoundBlaster Pro selects register 028h for 038h. SEE ALSO 039h Line In Level Right Read/Write ····················································· 02Eh Line In Level Read/Write ------------------------------------------------------------------------------ 039h Line In Level Right Read/Write SB16 LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Right Line In Level (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 000h NOTES ■ SoundBlaster 16 will automatically transfer bits 7-4 to bits 3-0 of register 02Eh. SEE ALSO 038h Line In Level Left Read/Write ····················································· 02Eh Line In Level Read/Write ------------------------------------------------------------------------------ 03Ah Microphone Level Read/Write SB16 LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┘ │ │ │ │ └─────────────┬─ Microphone Level (2dB) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 000h SEE ALSO 00Ah Microphone Level Read/Write ------------------------------------------------------------------------------ 03Bh PC Speaker Level Read/Write SB16 LEVEL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │[5]│[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┘ │ └─────────────────────────┬─ PC Speaker Level (2dB) └─────────────────────────────┘ DEFAULT N/A, 000h ------------------------------------------------------------------------------ 03Ch Output Control Read/Write SB16 CONTROL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Microphone (0 = Off, 1 = On) │ │ │ │ │ │ └─────── Right CD Audio (0 = Off, 1 = On) │ │ │ │ │ └─────────── Left CD Audio (0 = Off, 1 = On) │ │ │ │ └─────────────── Right Line In (0 = Off, 1 = On) │ │ │ └─────────────────── Left Line In (0 = Off, 1 = On) │ │ └─────────────────────┬─ Reserved (0) │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 01Fh SEE ALSO 041h Output Gain Control Left Read/Write 042h Output Gain Control Right Read/Write ····················································· 036h CD Audio Level Left Read/Write 037h CD Audio Level Right Read/Write 038h Line In Level Left Read/Write 039h Line In Level Right Read/Write 03Ah Microphone Level Read/Write ····················································· 00Eh Output/Stereo Select Read/Write ------------------------------------------------------------------------------ 03Dh Input Control Left Read/Write SB16 CONTROL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Microphone (0 = Off, 1 = On) │ │ │ │ │ │ └─────── Right CD Audio (0 = Off, 1 = On) │ │ │ │ │ └─────────── Left CD Audio (0 = Off, 1 = On) │ │ │ │ └─────────────── Right Line In (0 = Off, 1 = On) │ │ │ └─────────────────── Left Line In (0 = Off, 1 = On) │ │ └─────────────────────── Right FM (0 = Off, 1 = On) │ └─────────────────────────── Left FM (0 = Off, 1 = On) └─────────────────────────────── Reserved (0) DEFAULT N/A, 015h NOTES ■ Register controls remapping of left input channel (off, left, right, or left and right) SEE ALSO 03Eh Input Control Right Read/Write ····················································· 03Fh Input Gain Control Left Read/Write ····················································· 034h FM Level Left Read/Write 035h FM Level Right Read/Write 036h CD Audio Level Left Read/Write 037h CD Audio Level Right Read/Write 038h Line In Level Left Read/Write 039h Line In Level Right Read/Write 03Ah Microphone Level Read/Write ····················································· 00Ch Input/Filter Select Read/Write ------------------------------------------------------------------------------ 03Eh Input Control Right Read/Write SB16 CONTROL BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Microphone (0 = Off, 1 = On) │ │ │ │ │ │ └─────── Right CD Audio (0 = Off, 1 = On) │ │ │ │ │ └─────────── Left CD Audio (0 = Off, 1 = On) │ │ │ │ └─────────────── Right Line In (0 = Off, 1 = On) │ │ │ └─────────────────── Left Line In (0 = Off, 1 = On) │ │ └─────────────────────── Right FM (0 = Off, 1 = On) │ └─────────────────────────── Left FM (0 = Off, 1 = On) └─────────────────────────────── Reserved (0) DEFAULT N/A, 00Bh NOTES ■ Register controls remapping of right input channel (off, left, right, or left and right) ■ SoundBlaster Pro selects register 02Eh for 03Eh. SEE ALSO 03Dh Input Control Left Read/Write ····················································· 040h Input Gain Control Right Read/Write ····················································· 034h FM Level Left Read/Write 035h FM Level Right Read/Write 036h CD Audio Level Left Read/Write 037h CD Audio Level Right Read/Write 038h Line In Level Left Read/Write 039h Line In Level Right Read/Write 03Ah Microphone Level Read/Write ····················································· 00Ch Input/Filter Select Read/Write ------------------------------------------------------------------------------ 03Fh Input Gain Control Left Read/Write SB16 GAIN BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │[5]│[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┘ │ └─────────────────────────┬─ Left Input Gain Control (2^x) └─────────────────────────────┘ DEFAULT N/A, 000h SEE ALSO 040h Input Gain Control Right Read/Write ····················································· 043h Automatic Gain Control (AGC) Read/Write ····················································· 03Dh Input Control Left Read/Write ------------------------------------------------------------------------------ 040h Input Gain Control Right Read/Write SB16 GAIN BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │[5]│[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┘ │ └─────────────────────────┬─ Right Input Gain Control (2^x) └─────────────────────────────┘ DEFAULT N/A, 000h SEE ALSO 03Fh Input Gain Control Left Read/Write ····················································· 043h Automatic Gain Control (AGC) Read/Write ····················································· 03Dh Input Control Right Read/Write ------------------------------------------------------------------------------ 041h Output Gain Control Left Read/Write SB16 GAIN BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │[5]│[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┘ │ └─────────────────────────┬─ Left Output Gain Control (2^x) └─────────────────────────────┘ DEFAULT N/A, 000h NOTES ■ Output Gain Control has no effect when internal amplifier disabled. SEE ALSO 042h Output Gain Control Right Read/Write ····················································· 03Ch Output Control Read/Write ------------------------------------------------------------------------------ 042h Output Gain Control Right Read/Write SB16 GAIN BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │[5]│[4]│[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┘ │ └─────────────────────────┬─ Right Output Gain Control (2^x) └─────────────────────────────┘ DEFAULT N/A, 000h NOTES ■ Output Gain Control has no effect when internal amplifier disabled. SEE ALSO 041h Output Gain Control Left Read/Write ····················································· 03Ch Output Control Read/Write ------------------------------------------------------------------------------ 043h Automatic Gain Control (AGC) Read/Write SB16 AGC BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│[3]│[2]│[1]│ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Automatic Gain Control (1 = Enable) │ │ │ │ │ │ └─────┬─ Reserved (0) │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 000h NOTES ■ Automatic Gain Control automatically maximizes input signal strength. SEE ALSO 03Fh Input Gain Control Left Read/Write 040h Input Gain Control Right Read/Write ------------------------------------------------------------------------------ 044h Treble Left Read/Write SB16 TREBLE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────┬─ Treble Left (2dB, -14dB to 14dB) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 080h SEE ALSO 045h Treble Right Read/Write ····················································· 046h Bass Left Read/Write ------------------------------------------------------------------------------ 045h Treble Right Read/Write SB16 TREBLE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────┬─ Treble Right (2dB, -14dB to 14dB) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 080h SEE ALSO 044h Treble Left Read/Write ····················································· 047h Bass Right Read/Write ------------------------------------------------------------------------------ 046h Bass Left Read/Write SB16 BASS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────┬─ Bass Left (2dB, -14dB to 14dB) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 080h SEE ALSO 047h Bass Right Read/Write ····················································· 044h Treble Left Read/Write ------------------------------------------------------------------------------ 047h Bass Right Read/Write SB16 BASS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │[3]│[2]│[1]│[0]║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Reserved (0) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────┬─ Bass Right (2dB, -14dB to 14dB) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ DEFAULT N/A, 080h SEE ALSO 046h Bass Left Read/Write ····················································· 045h Treble Right Read/Write ------------------------------------------------------------------------------ 080h IRQ Select Read/Write SB16 SELECT BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── IRQ2 (0 = Disable, 1 = Enable) │ │ │ │ │ │ └─────── IRQ5 (0 = Disable, 1 = Enable) │ │ │ │ │ └─────────── IRQ7 (0 = Disable, 1 = Enable) │ │ │ │ └─────────────── IRQ10 (0 = Disable, 1 = Enable) │ │ │ └─────────────────┬─ Reserved (1) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Unaffected by mixer reset or soft reboot. ■ Enabling multiple bits enables multiple IRQs. SEE ALSO 081h DMA Select Read/Write ····················································· 082h IRQ Status Read ------------------------------------------------------------------------------ 081h DMA Select Read/Write SB16 SELECT BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │[4]│ 3 │[2]│ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── DMA0, 8-bit (0 = Disable, 1 = Enable) │ │ │ │ │ │ └─────── DMA1, 8-bit (0 = Disable, 1 = Enable) │ │ │ │ │ └─────────── DMA2, Reserved (0) │ │ │ │ └─────────────── DMA3, 8-bit (0 = Disable, 1 = Enable) │ │ │ └─────────────────── DMA4, Reserved (0) │ │ └─────────────────────── DMA5, 16-bit (0 = Disable, 1 = Enable) │ └─────────────────────────── DMA6, 16-bit (0 = Disable, 1 = Enable) └─────────────────────────────── DMA7, 16-bit (0 = Disable, 1 = Enable) NOTES ■ Unaffected by mixer reset or soft reboot. ■ Enabling multiple 8 or 16-bit DMA bits enables multiple DMA channels. ■ Disabling all 8-bit DMA channel bits disables 8-bit DMA requests, including translated 16-bit DMA requests. ■ Disabling all 16-bit DMA channel bits enables translation of 16-bit DMA requests to 8-bit ones, using the selected 8-bit DMA channel. SEE ALSO 080h IRQ Select Read/Write ------------------------------------------------------------------------------ 082h IRQ Status Read SB16 STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │[3]│ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── IRQ Status, 8-bit (1 = Active) │ │ │ │ │ │ └─────── IRQ Status, 16-bit (1 = Active) │ │ │ │ │ └─────────── IRQ Status, MPU-401 (1 = Active) │ │ │ │ └─────────────── Reserved (0) │ │ │ └─────────────────┬─ ??? │ │ └─────────────────────┤ (01h = v4.04, 02h = v4.05, 08h = v4.12) │ └─────────────────────────┤ └─────────────────────────────┘ SEE ALSO 080h IRQ Select Read/Write ============================================================================== DMA CONTROLLERS ------------------------------------------------------------------------------ ┌-────────┐ ┌──┬┬──┐ ┌──┬┬──┐ │ ┌─────┐ │ ╒╡ └┘ ╞╕─Channel 4──╒╡ └┘ ╞╕─── Channel 0 ┐ │ │ CPU │ │────╒╡ DMA2 ╞╕──────────┐ ╒╡ DMA1 ╞╕─── Channel 1 ├ 8-bit │ └─────┘ │ ╒╡ 8237 ╞╕────────┐ │ ╒╡ 8237 ╞╕─── Channel 2 │ └────────┘ ╒╡ ╞╕──────┐ │ │ ╒╡ ╞╕─── Channel 3 ┘ └──────┘ │ │ │ └──────┘ │ │ └────────────── Channel 5 ┐ DMAC ORGANIZATION (AT) │ └──────────────── Channel 6 ├ 16-bit └────────────────── Channel 7 ┘ ───────────────────────────────────────────────────────────────────────────── ╔═══════════════╤═════════════════╤═════════════════╗ ║ DMA CHANNEL │ AT ARCHITECTURE │ XT ARCHITECTURE ║ ║ │ │ ║ ╠═══════════════╪═════════════════╪═════════════════╣ ┐ ║ 0 │ AVAILABLE │ DRAM REFRESH ║ │ ╟───────────────┼─────────────────┼─────────────────╢ ├ Memory-Memory support ║ 1 │ AVAILABLE │ AVAILABLE ║ │ ╟───────────────┼─────────────────┼─────────────────╢ ┘ ║ 2 │ FLOPPY CONTRLR. │ FLOPPY CONTRLR. ║ ╟───────────────┼─────────────────┼─────────────────╢ ║ 3 │ AVAILABLE │ HDD CONTROLLER ║ ╟---------------┼-----------------┼-----------------╢ ║ 4 │ CASCADE │ N/A ║ ╟───────────────┼─────────────────┼─────────────────╢ ║ 5 │ AVAILABLE │ N/A ║ ╟───────────────┼─────────────────┼─────────────────╢ ║ 6 │ AVAILABLE │ N/A ║ ╟───────────────┼─────────────────┼─────────────────╢ ║ 7 │ AVAILABLE │ N/A ║ ╚═══════════════╧═════════════════╧═════════════════╝ ───────────────────────────────────────────────────────────────────────────── PROCEDURE ───────────────────────────────────────────────────────────────────────────── 1) Enable channel mask OUT 00Ah,004h OR cChannel ( 8-bit) ····················································· OUT 0D4h,004h OR cChannel (16-bit) 2) Clear byte pointer OUT 00Ch,... ( 8-bit) ····················································· OUT 0D8h,... (16-bit) 3) Configure transfer mode OUT 00Bh,cMode OR cChannel ( 8-bit) ····················································· OUT 0D6h,cMode OR cChannel (16-bit) 4) Write page address OUT { 087h,083h,081h,082h },cPage ( 8-bit) ····················································· OUT { 08Fh,08Bh,089h,08Ah },cPage (16-bit) 5) Write offset address OUT { 000h,002h,004h,006h },cAddressLo ( 8-bit) OUT { 000h,002h,004h,006h },cAddressHi ····················································· OUT { 0C0h,0C4h,0C8h,0CCh },cAddressLo (16-bit) OUT { 0C0h,0C4h,0C8h,0CCh },cAddressHi 6) Write length - 1 OUT { 001h,003h,005h,007h },cLengthLo ( 8-bit) OUT { 001h,003h,005h,007h },cLengthHi ····················································· OUT { 0C2h,0C6h,0CAh,0CEh },cLengthLo (16-bit) OUT { 0C2h,0C6h,0CAh,0CEh },cLengthHi 7) Disable channel mask OUT 00Ah,cChannel ( 8-bit) ····················································· OUT 0D4h,cChannel (16-bit) ------------------------------------------------------------------------------ 000h Channel 0 Address, 8-bit Read/Write XT DESCRIPTION Programs channel transfer offset address (byte granular). PROCEDURE a) Output LSB of offset address (port 000h) b) Output MSB of offset address (port 000h) NOTES ■ Reading port retrieves current transfer offset address. SEE ALSO 087h Channel 0 Page, 8-bit Write 001h Channel 0 Length, 8-bit Read/Write ------------------------------------------------------------------------------ 001h Channel 0 Length, 8-bit Read/Write XT DESCRIPTION Programs channel transfer length. PROCEDURE a) Output LSB of length (port 001h) b) Output MSB of length (port 001h) LENGTH = BYTES - 1 NOTES ■ Reading port retrieves transfer length remaining. SEE ALSO 087h Channel 0 Page, 8-bit Write 000h Channel 0 Address, 8-bit Read/Write ------------------------------------------------------------------------------ 002h Channel 1 Address, 8-bit Read/Write XT DESCRIPTION Programs channel transfer offset address (byte granular). PROCEDURE a) Output LSB of offset address (port 002h) b) Output MSB of offset address (port 002h) NOTES ■ Reading port retrieves current transfer offset address. SEE ALSO 083h Channel 1 Page, 8-bit Write 003h Channel 1 Length, 8-bit Read/Write ------------------------------------------------------------------------------ 003h Channel 1 Length, 8-bit Read/Write XT DESCRIPTION Programs channel transfer length. PROCEDURE a) Output LSB of length (port 003h) b) Output MSB of length (port 003h) LENGTH = BYTES - 1 NOTES ■ Reading port retrieves transfer length remaining. SEE ALSO 083h Channel 1 Page, 8-bit Write 002h Channel 1 Address, 8-bit Read/Write ------------------------------------------------------------------------------ 004h Channel 2 Address, 8-bit Read/Write XT DESCRIPTION Programs channel transfer offset address (byte granular). PROCEDURE a) Output LSB of offset address (port 004h) b) Output MSB of offset address (port 004h) NOTES ■ Reading port retrieves current transfer offset address. SEE ALSO 081h Channel 2 Page, 8-bit Write 005h Channel 2 Length, 8-bit Read/Write ------------------------------------------------------------------------------ 005h Channel 2 Length, 8-bit Read/Write XT DESCRIPTION Programs channel transfer length. PROCEDURE a) Output LSB of length (port 005h) b) Output MSB of length (port 005h) LENGTH = BYTES - 1 NOTES ■ Reading port retrieves transfer length remaining. SEE ALSO 081h Channel 2 Page, 8-bit Write 004h Channel 2 Address, 8-bit Read/Write ------------------------------------------------------------------------------ 006h Channel 3 Address, 8-bit Read/Write XT DESCRIPTION Programs channel transfer offset address (byte granular). PROCEDURE a) Output LSB of offset address (port 006h) b) Output MSB of offset address (port 006h) NOTES ■ Reading port retrieves current transfer offset address. SEE ALSO 082h Channel 3 Page, 8-bit Write 007h Channel 3 Length, 8-bit Read/Write ------------------------------------------------------------------------------ 007h Channel 3 Length, 8-bit Read/Write XT DESCRIPTION Programs channel transfer length. PROCEDURE a) Output LSB of length (port 007h) b) Output MSB of length (port 007h) LENGTH = BYTES - 1 NOTES ■ Reading port retrieves transfer length remaining. SEE ALSO 082h Channel 3 Page, 8-bit Write 006h Channel 3 Address, 8-bit Read/Write ------------------------------------------------------------------------------ 008h Status Register, 8-bit Read XT DESCRIPTION Controller channel status register. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Channel 0 Terminal Count (1 = Reached) │ │ │ │ │ │ └─────── Channel 1 Terminal Count (1 = Reached) │ │ │ │ │ └─────────── Channel 2 Terminal Count (1 = Reached) │ │ │ │ └─────────────── Channel 3 Terminal Count (1 = Reached) │ │ │ └─────────────────── Channel 0 DREQ (1 = Active ) │ │ └─────────────────────── Channel 1 DREQ (1 = Active ) │ └─────────────────────────── Channel 2 DREQ (1 = Active ) └─────────────────────────────── Channel 3 DREQ (1 = Active ) NOTES ■ Terminal count bit indicates transfer complete. ------------------------------------------------------------------------------ 008h Command Register, 8-bit Write XT DESCRIPTION Controller configuration register. COMMAND BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Mem-Mem Transfer (1 = Enable) │ │ │ │ │ │ └─────── Channel 0-4 Address Hold (1 = Enable) │ │ │ │ │ └─────────── Controller (0 = Enable, 1 = Disable) │ │ │ │ └─────────────── Timing (0 = Normal, 1 = Compressed) │ │ │ └─────────────────── Priority (0 = Fixed, 1 = Rotating) │ │ └─────────────────────── Write Mode (0 = Late, 1 = Extended) │ └─────────────────────────── DREQ Active Sensing (0 = Low, 1 = High) └─────────────────────────────── DACK Active Sensing (0 = Low, 1 = High) ------------------------------------------------------------------------------ 009h Request Register, 8-bit Write XT DESCRIPTION ??? REQUEST BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│[3]│ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Channel Select │ │ │ │ │ │ └─────┘ │ │ │ │ │ └─────────── Channel Request (1 = Enable) │ │ │ │ └─────────────┬─ Reserved (0) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ ------------------------------------------------------------------------------ 00Ah Single Mask Register, 8-bit Write XT DESCRIPTION Selects individual DMA channel, and enables or disables it. MASK BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│[3]│ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Channel Select │ │ │ │ │ │ └─────┘ │ │ │ │ │ └─────────── Channel Mask (0 = Clear, 1 = Set) │ │ │ │ └─────────────┬─ Reserved (0) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Program the mask register before programming channel. SEE ALSO 00Fh Master Mask Register, 8-bit Write ------------------------------------------------------------------------------ 00Bh Mode Register, 8-bit Write XT DESCRIPTION Selects and configures individual DMA channel. MODE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Channel Select │ │ │ │ │ │ └─────┘ │ │ │ │ │ └─────────┬─ Operation (0 = Verify, │ │ │ │ └─────────────┘ 1 = Write, 2 = Read) │ │ │ └─────────────────── Auto-Initialize (0 = Off, 1 = On) │ │ └─────────────────────── Direction (0 = Increment) │ └─────────────────────────┬─ Operation Mode (0 = Demand,1 = Single, └─────────────────────────────┘ 2 = Block, 3 = Cascade) NOTES ■ Demand mode ╓───────┐ ┌──────────────────┐ ┌───┐ ┌──────┐ ┌───────╖ ║ DREQ ├───┤ TERMINAL COUNT-1 ├──┤ ? ├──│ DACK ├───│ DONE ║ ╙──────┬┘Y └──────────────────┘ └─┬─┘N └──┬──┬┘ └───────╜ └──┘N │ │Y └──┘N │Y │ ┌────┐ ┌─┴─┐ │ └───────────┤DREQ│────┤EOP├────────┘ Y└───┬┘ N└───┘Y └──┘N Transfer begins as soon as DREQ becomes active and continues until terminal count is reached or an external end-of-process (EOP) is signalled. In auto-initialized mode, only an external EOP stops the transfer. Deactivating DREQ pauses the transfer, reactivating it continues. ■ Single mode ╓───────┐ ┌──────────────────┐ ┌───┐ ┌───────╖ ║ DREQ ├───┤ TERMINAL COUNT-1 ├──┤ ? ├─────────────│ DONE ║ ╙───────┘ └──────────────────┘ └─┬─┘N └───────╜ │ │Y │ ┌──────┐ ┌────┐ │ └─┤ DACK │──┤DREQ│──────┘ Y└───┬──┘ Y└───┬┘ └──┘N └──┘N Transfer begins as soon as DREQ becomes active and continues until the next byte is transferred and loops until terminal count. ■ Block mode ╓───────┐ ┌──────────────────┐ ┌───┐ ┌──────┐ ┌───────╖ ║ DREQ ├───┤ TERMINAL COUNT-1 ├──┤ ? ├──│ DACK ├───│ DONE ║ ╙──────┬┘Y └──────────────────┘ └─┬─┘N └──┬──┬┘ └───────╜ └──┘N │ │Y └──┘N │Y │ ┌─┴─┐ │ └─────────────────────┤EOP├────────┘ N└───┘Y Transfer begins as soon as DREQ becomes active and continues until terminal count is reached or an external end-of-process (EOP) is signalled. In auto-initialized mode, only an external EOP stops the transfer. ■ Cascade mode Reserved for chaining DMA controllers. ------------------------------------------------------------------------------ 00Ch Clear Byte Pointer Register, 8-bit Write XT DESCRIPTION Resets 8-bit DMA controller address pointer on output (any value). ------------------------------------------------------------------------------ 00Dh Temporary Register, 8-bit Read XT DESCRIPTION Contains memory-to-memory data bytes. ------------------------------------------------------------------------------ 00Dh Master Reset Register, 8-bit Write XT DESCRIPTION Resets 8-bit DMA controller and all its channels on output (any value). SEE ALSO 00Eh Master Enable Register, 8-bit Write ------------------------------------------------------------------------------ 00Eh Master Enable Register, 8-bit Write XT DESCRIPTION Enables all 8-bit DMA controller channels on output (any value). SEE ALSO 00Dh Master Reset Register, 8-bit Write ------------------------------------------------------------------------------ 00Fh Master Mask Register, 8-bit Write XT DESCRIPTION Selects multiple DMA channels, enabling or disabling them. MASK BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Channel 0 (0 = Enable, 1 = Disable) │ │ │ │ │ │ └─────── Channel 1 (0 = Enable, 1 = Disable) │ │ │ │ │ └─────────── Channel 2 (0 = Enable, 1 = Disable) │ │ │ │ └─────────────── Channel 3 (0 = Enable, 1 = Disable) │ │ │ └─────────────────┬─ Reserved (0) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ SEE ALSO 00Ah Single Mask Register, 8-bit Write ------------------------------------------------------------------------------ 081h Channel 2 Page, 8-bit Write XT DESCRIPTION Programs channel page address. PAGE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Page, Channel 2 (64K granular) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────┬─ Reserved (0) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Page addressing allows access to 1M of physical memory with 8-bit DMA. SEE ALSO 004h Channel 2 Address, 8-bit Read/Write 005h Channel 2 Length, 8-bit Read/Write ------------------------------------------------------------------------------ 082h Channel 3 Page, 8-bit Write XT DESCRIPTION Programs channel page address. PAGE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Page, Channel 3 (64K granular) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────┬─ Reserved (0) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Page addressing allows access to 1M of physical memory with 8-bit DMA. SEE ALSO 006h Channel 3 Address, 8-bit Read/Write 007h Channel 3 Length, 8-bit Read/Write ------------------------------------------------------------------------------ 083h Channel 1 Page, 8-bit Write XT DESCRIPTION Programs channel page address. PAGE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Page, Channel 1 (64K granular) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────┬─ Reserved (0) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Page addressing allows access to 1M of physical memory with 8-bit DMA. SEE ALSO 002h Channel 1 Address, 8-bit Read/Write 003h Channel 1 Length, 8-bit Read/Write ------------------------------------------------------------------------------ 087h Channel 0 Page, 8-bit Write XT DESCRIPTION Programs channel page address. PAGE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Page, Channel 0 (64K granular) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┘ │ │ │ └─────────────────┬─ Reserved (0) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Page addressing allows access to 1M of physical memory with 8-bit DMA. SEE ALSO 000h Channel 0 Address, 8-bit Read/Write 001h Channel 0 Length, 8-bit Read/Write ------------------------------------------------------------------------------ 089h Channel 6 Page, 16-bit Write AT DESCRIPTION Programs channel page address. PAGE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Page, Channel 6 (128K granular) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Page addressing allows access to 16M of physical memory with 16-bit DMA. SEE ALSO 0C8h Channel 6 Address, 16-bit Read/Write 0CAh Channel 6 Length, 16-bit Read/Write ------------------------------------------------------------------------------ 08Ah Channel 7 Page, 16-bit Write AT DESCRIPTION Programs channel page address. PAGE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Page, Channel 7 (128K granular) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Page addressing allows access to 16M of physical memory with 16-bit DMA. SEE ALSO 0CCh Channel 7 Address, 16-bit Read/Write 0CEh Channel 7 Length, 16-bit Read/Write ------------------------------------------------------------------------------ 08Bh Channel 5 Page, 16-bit Write AT DESCRIPTION Programs channel page address. PAGE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Page, Channel 5 (128K granular) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Page addressing allows access to 16M of physical memory with 16-bit DMA. SEE ALSO 0C4h Channel 5 Address, 16-bit Read/Write 0C6h Channel 5 Length, 16-bit Read/Write ------------------------------------------------------------------------------ 08Fh Channel 4 Page, 16-bit Write AT DESCRIPTION Programs channel page address. PAGE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Page, Channel 4 (128K granular) │ │ │ │ │ │ └─────┤ │ │ │ │ │ └─────────┤ │ │ │ │ └─────────────┤ │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Reserved channel for cascading DMA controllers. ■ Page addressing allows access to 16M of physical memory with 16-bit DMA. SEE ALSO 0C0h Channel 4 Address, 16-bit Read/Write 0C2h Channel 4 Length, 16-bit Read/Write ------------------------------------------------------------------------------ 0C0h Channel 4 Address, 16-bit Read/Write AT DESCRIPTION Programs channel transfer offset address (word granular). PROCEDURE a) Output LSB of offset address/2 (port 0C0h) b) Output MSB of offset address/2 (port 0C0h) NOTES ■ Reading port retrieves current transfer offset address. SEE ALSO 08Fh Channel 4 Page, 16-bit Write 0C2h Channel 4 Length, 16-bit Read/Write ------------------------------------------------------------------------------ 0C2h Channel 4 Length, 16-bit Read/Write AT DESCRIPTION Programs channel transfer length. PROCEDURE a) Output LSB of length (port 0C2h) b) Output MSB of length (port 0C2h) LENGTH = BYTES/2 - 1 NOTES ■ Reading port retrieves transfer length remaining. SEE ALSO 08Fh Channel 4 Page, 16-bit Write 0C0h Channel 4 Address, 16-bit Read/Write ------------------------------------------------------------------------------ 0C4h Channel 5 Address, 16-bit Read/Write AT DESCRIPTION Programs channel transfer offset address (word granular). PROCEDURE a) Output LSB of offset address/2 (port 0C4h) b) Output MSB of offset address/2 (port 0C4h) NOTES ■ Reading port retrieves current transfer offset address. SEE ALSO 08Bh Channel 5 Page, 16-bit Write 0C6h Channel 5 Length, 16-bit Read/Write ------------------------------------------------------------------------------ 0C6h Channel 5 Length, 16-bit Read/Write AT DESCRIPTION Programs channel transfer length. PROCEDURE a) Output LSB of length (port 0C6h) b) Output MSB of length (port 0C6h) LENGTH = BYTES/2 - 1 NOTES ■ Reading port retrieves transfer length remaining. SEE ALSO 08Bh Channel 5 Page, 16-bit Write 0C4h Channel 5 Address, 16-bit Read/Write ------------------------------------------------------------------------------ 0C8h Channel 6 Address, 16-bit Read/Write AT DESCRIPTION Programs channel transfer offset address (word granular). PROCEDURE a) Output LSB of offset address/2 (port 0C8h) b) Output MSB of offset address/2 (port 0C8h) NOTES ■ Reading port retrieves current transfer offset address. SEE ALSO 089h Channel 6 Page, 16-bit Write 0CAh Channel 6 Length, 16-bit Read/Write ------------------------------------------------------------------------------ 0CAh Channel 6 Length, 16-bit Read/Write AT DESCRIPTION Programs channel transfer length. PROCEDURE a) Output LSB of length (port 0CAh) b) Output MSB of length (port 0CAh) LENGTH = BYTES/2 - 1 NOTES ■ Reading port retrieves transfer length remaining. SEE ALSO 089h Channel 6 Page, 16-bit Write 0C8h Channel 6 Address, 16-bit Read/Write ------------------------------------------------------------------------------ 0CCh Channel 7 Address, 16-bit Read/Write AT DESCRIPTION Programs channel transfer offset address (word granular). PROCEDURE a) Output LSB of offset address/2 (port 0CEh) b) Output MSB of offset address/2 (port 0CEh) NOTES ■ Reading port retrieves current transfer offset address. SEE ALSO 08Ah Channel 7 Page, 16-bit Write 0CEh Channel 7 Length, 16-bit Read/Write ------------------------------------------------------------------------------ 0CEh Channel 7 Length, 16-bit Read/Write AT DESCRIPTION Programs channel transfer length. PROCEDURE a) Output LSB of length (port 0CEh) b) Output MSB of length (port 0CEh) LENGTH = BYTES/2 - 1 NOTES ■ Reading port retrieves transfer length remaining. SEE ALSO 08Ah Channel 7 Page, 16-bit Write 0CCh Channel 7 Address, 16-bit Read/Write ------------------------------------------------------------------------------ 0D0h Status Register, 16-bit Read AT DESCRIPTION Controller channel status register. STATUS BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Channel 4 Terminal Count (1 = Reached) │ │ │ │ │ │ └─────── Channel 5 Terminal Count (1 = Reached) │ │ │ │ │ └─────────── Channel 6 Terminal Count (1 = Reached) │ │ │ │ └─────────────── Channel 7 Terminal Count (1 = Reached) │ │ │ └─────────────────── Channel 4 DREQ (1 = Active ) │ │ └─────────────────────── Channel 5 DREQ (1 = Active ) │ └─────────────────────────── Channel 6 DREQ (1 = Active ) └─────────────────────────────── Channel 7 DREQ (1 = Active ) NOTES ■ Terminal count bit indicates transfer complete. ------------------------------------------------------------------------------ 0D0h Command Register, 16-bit Write AT DESCRIPTION Controller configuration register. COMMAND BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Mem-Mem Transfer (1 = Enable) │ │ │ │ │ │ └─────── Channel 0-4 Address Hold (1 = Enable) │ │ │ │ │ └─────────── Controller (0 = Enable, 1 = Disable) │ │ │ │ └─────────────── Timing (0 = Normal, 1 = Compressed) │ │ │ └─────────────────── Priority (0 = Fixed, 1 = Rotating) │ │ └─────────────────────── Write Mode (0 = Late, 1 = Extended) │ └─────────────────────────── DREQ Active Sensing (0 = Low, 1 = High) └─────────────────────────────── DACK Active Sensing (0 = Low, 1 = High) ------------------------------------------------------------------------------ 0D2h Request Register, 16-bit Write AT DESCRIPTION ??? REQUEST BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│[3]│ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Channel Select (-4) │ │ │ │ │ │ └─────┘ │ │ │ │ │ └─────────── Channel Request (1 = Enable) │ │ │ │ └─────────────┬─ Reserved (0) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ ------------------------------------------------------------------------------ 0D4h Single Mask Register, 16-bit Write AT DESCRIPTION Selects individual DMA channel, and enables or disables it. MASK BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│[3]│ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Channel Select (-4) │ │ │ │ │ │ └─────┘ │ │ │ │ │ └─────────── Channel Mask (0 = Clear, 1 = Set) │ │ │ │ └─────────────┬─ Reserved (0) │ │ │ └─────────────────┤ │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ NOTES ■ Program the mask register before programming channel. SEE ALSO 0DEh Master Mask Register, 16-bit Write ------------------------------------------------------------------------------ 0D6h Mode Register, 16-bit Write AT DESCRIPTION Selects and configures individual DMA channel. MODE BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─┬─ Channel Select (-4) │ │ │ │ │ │ └─────┘ │ │ │ │ │ └─────────┬─ Operation (0 = Verify, │ │ │ │ └─────────────┘ 1 = Write, 2 = Read) │ │ │ └─────────────────── Auto-Initialize (0 = Off, 1 = On) │ │ └─────────────────────── Direction (0 = Increment) │ └─────────────────────────┬─ Operation Mode (0 = Demand,1 = Single, └─────────────────────────────┘ 2 = Block, 3 = Cascade) NOTES ■ See register 00Bh notes for description of modes. ------------------------------------------------------------------------------ 0D8h Clear Byte Pointer Register, 16-bit Write AT DESCRIPTION Resets 16-bit DMA controller address pointer on output (any value). ------------------------------------------------------------------------------ 0DAh Temporary Register, 16-bit Read AT DESCRIPTION Contains memory-to-memory data words. NOTES ■ Reserved for cascading DMA controllers on AT architecture. ------------------------------------------------------------------------------ 0DAh Master Reset Register, 16-bit Write AT DESCRIPTION Resets 16-bit DMA controller and all its channels on output (any value). SEE ALSO 0DCh Master Enable Register, 16-bit Write ------------------------------------------------------------------------------ 0DCh Master Enable Register, 16-bit Write AT DESCRIPTION Enables all 16-bit DMA controller channels on output (any value). SEE ALSO 0DAh Master Reset Register, 16-bit Write ------------------------------------------------------------------------------ 0DEh Master Mask Register, 16-bit Write AT DESCRIPTION Selects multiple DMA channels, enabling or disabling them. MASK BYTE ╔═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗ ║[7]│[6]│[5]│[4]│ 3 │ 2 │ 1 │ 0 ║ ╚═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╧═╤═╝ │ │ │ │ │ │ │ └─── Channel 4 (0 = Enable, 1 = Disable) │ │ │ │ │ │ └─────── Channel 5 (0 = Enable, 1 = Disable) │ │ │ │ │ └─────────── Channel 6 (0 = Enable, 1 = Disable) │ │ │ │ └─────────────── Channel 7 (0 = Enable, 1 = Disable) │ │ │ └─────────────────┬─ Reserved (0) │ │ └─────────────────────┤ │ └─────────────────────────┤ └─────────────────────────────┘ SEE ALSO 0D4h Single Mask Register, 16-bit Write ============================================================================== GLOSSARY ------------------------------------------------------------------------------ Adaptive Differential Pulse Code Modulation (ADPCM) Creative Labs ADPCM does not follow the CCITT ADPCM recommendations, but does provide a similar quality compression scheme for 8-bit samples (down to 2, 2.6, or 4-bits per sample). Creative Labs ADPCM is not supported by many SoundBlaster clones. ············································································· Advanced Signal Processor (ASP, CSP) Creative Labs proprietary programmable signal processor. Although development tools for the ASP are scarce, Creative Labs has released demo software implementing QSound technology and various compression schemes (from IMA ADPCM to µ-law and α-law). Recently renamed from ASP to CSP (Creative Signal Processor) to avoid confusion with a U.S. company of the same name. ············································································· Aliasing Digital artifacts indicative of finite numerical representation, especially noticeble at areas of high deviation. ············································································· Amplitude Maximum departure of the value of an alternating current or wave from an average value. In acoustics, amplitude is intimately related to loudness. ············································································· Amplitude Modulation (AM) Carrier wave amplitude modulation in response to the strength of a signal. ············································································· Analog Representation with periodic waves. Contrast digital. ············································································· Analog-To-Digital Convertor (ADC) Device which converts from an analog signal (such as sound) to a digital one. ············································································· Auto-Initialize Mode (AI) Mode where DMA controller processes multiple blocks without explicit reprogramming. Contrast single-cycle mode. ············································································· Bass Acoustic quality describing sounds of lower frequency in the spectrum. ············································································· Creative Music Synthesis??? (C/MS) Obsolete AM synthesizer chipset implementing twelve stereo sine generators modulated in predefined banks by one of four programmable noise generators. Originally implemented on the Creative Labs GameBlaster card; supported by the SoundBlaster 1.0 and 1.5 (as an upgrade option). ············································································· Decibel (dB) Unit of measurement describing the ratio of two acoustic, mechanical, or electrical signal strengths; expressed as ten times the common logarithm of their power ratio. ············································································· Digital Representation with finite numerical elements. Contrast analog. ············································································· Digital Signal Processor (DSP) Device which performs mathematical operations across a digital waveform. SoundBlasters barely qualify, with only ADPCM to their name. ············································································· Digital-To-Analog Convertor (DAC) Device which converts from a digital signal to an analog one. ············································································· Direct Memory Access (DMA) Method of using external hardware to perform block memory copy operations so the central processing unit can be dedicated to more sophisticated tasks. ············································································· Frequency Number of repetitive occurences, or cycles, within a given time domain. ············································································· Frequency Modulation (FM) Carrier wave frequency modulation in response to a signal; resulting in decreased distortion levels. ············································································· Frequency Modulation Synthesis (FM Synthesis) Describes a method of synthesizing sound using a programmable carrier and one or more programmable frequency modulators. Popularized by Fairlight. Yamaha OPL-hardware implementation is closer to phase modulation. ············································································· Gain Ratio of increase of input over output in an amplifier. ············································································· General MIDI Standardized 128-entry patch map and associated specifications. Patch quality differs greatly across implementations. Regulated by the MIDI Manufacturer's Association (MMA). ············································································· Hertz (Hz) Unit of frequency measurement describing number of cycles per second. ············································································· High Speed Mode SoundBlaster DMA transfer mode operating at a frequency greater than 23kHz, using up clocks cycles otherwise destined for DSP command interpretation. Obsolete on SoundBlaster 16, but supported. (unofficial) ············································································· Mixer SoundBlaster component analagous to an army of volume controls. ············································································· MPU-401 Developed by Roland, the MPU-401 is the industry standard MIDI interface. It can operate either as an intelligent or a dumb UART. ············································································· Music Instrument Digital Interface (MIDI) Standard for communication between electronic musical instruments, related hardware, and digital computers. Serial protocol operating at 38.4Kbps. ············································································· Nyquist Theorem Accurate reproduction of a signal demands that the sampling frequency be at least twice the rate of the highest frequency in the source signal. ············································································· Pulse Code Modulation (PCM) Digital sound reproduction method that outputs discrete amplitude values at a steady rate to produce an analog sound. ············································································· QSound (tm) Filtering technique providing a larger panning arc than traditional stereo techniques (180°). Licensed by Creative Labs. ············································································· Sample Digital representation of analog signal. ············································································· Single Cycle Mode (SC) Mode where DMA controller processes a single block. Contrast auto-init mode. ············································································· Treble Acoustic quality describing sounds of higher frequency in the spectrum. ············································································· Universal Asynchronous Receiver/Transmitter (UART) Device responsible for conversion to or from a serial bit stream. ············································································· Wave Table Synthesis Synthesis method employing sampled instruments and sounds as opposed to artifically generated sound effects. ············································································· ============================================================================== ACKNOWLEDGEMENTS ------------------------------------------------------------------------------ Ron Arts, Chris Barrett, Hussam Eassa, Brandom Hume, Cornel Huth, Draeden/VLA, Jeffery Lee, Alain Jacques, Jerry Joplin, Eckard Lehmann, Juan Carlos Leon, Bob Manson, Tom Marshall, Richard Mulder, Josha Munnik, Eric Oostendorp, Tino Riethmueller, Jim Roberts, Peter Roberts, Jens-Uwe Rumstich, Daniel Sachs, Edward Schlunder, Peter Sprenger, Heiko Stassburg, Mark Stehr, Jim Vieira ============================================================================== REFERENCES ------------------------------------------------------------------------------ STANDARDS ──────────────────────────────────────────────────────────────────────────── CCITT G.721 - ADPCM @ 32 kbits/sec CCITT G.723 - ADPCM @ 24 and 40 kbits/sec ──────────────────────────────────────────────────────────────────────────── PUBLICATIONS ──────────────────────────────────────────────────────────────────────────── MIDI Processing Unit MPU-401 Technical Reference v1.5 Roland Corporation Roland Corp. 1985 ──────────────────────────────────────────────────────────────────────────── Schaum's Outline: Theory and Problems of Acoustics William Seto McGraw-Hill 1971 ──────────────────────────────────────────────────────────────────────────── Yamaha OPL2 Technical Reference CAT#: LSI-6MF2622 Yamaha Corporation Yamaha Corp. +1 408 437-3133 (USA) ──────────────────────────────────────────────────────────────────────────── Yamaha OPL3 Technical Reference CAT#: LSI-2438120 Yamaha Corporation Yamaha Corp. +1 408 437-3133 (USA) ──────────────────────────────────────────────────────────────────────────── BOOKS ──────────────────────────────────────────────────────────────────────────── The SoundBlaster Book ISBN: 3-88745-560-6 Josha Munnik, Eric Oostendorp SYBEX 1992 ──────────────────────────────────────────────────────────────────────────── Das SoundBlaster Profibuch ISBN: 3-89319-583-1 Eckard Lehmann, Tino Riethmueller, Heiko Stassburg Addison-Wesley 1993 ──────────────────────────────────────────────────────────────────────────── FILES ──────────────────────────────────────────────────────────────────────────── Audio File Formats FAQ AudioFormats.* Guido van Rossum ftp.cwi.nl::pub/audio TEXT ──────────────────────────────────────────────────────────────────────────── DMA Programming Information VLA_DMA.ZIP 3K Draeden/VLA 1993 x2ftp.oulu.fi::pub/msdos/programming/vla TEXT ──────────────────────────────────────────────────────────────────────────── Joystick Programming Information GAMEPORT.INF 3K Bill Frolik 1990 x2ftp.oulu.fi::pub/msdos/programming/specs TEXT ──────────────────────────────────────────────────────────────────────────── MIDI Standards Documentation MIDI*.* Various ftp.cs.ruu.nl::/pub/MIDI/DOC TEXT ──────────────────────────────────────────────────────────────────────────── OPL2 Programming Information ADLIB_SB.TXT 20K Jeffery Lee 1992 x2ftp.oulu.fi::pub/msdos/programming/faq TEXT ──────────────────────────────────────────────────────────────────────────── OPL3 Programming Information OPL3_DOC.ARJ 18K Vladimir Arnost 1994 x2ftp.oulu.fi::pub/msdos/programming/docs TEXT, GIF ──────────────────────────────────────────────────────────────────────────── PC Game Programmer's Enyclopedia v1.0 PCGPE10.ZIP 702K Mark Feldman 1994 x2ftp.oulu.fi::pub/msdos/programming/gpe TEXT, PASCAL ──────────────────────────────────────────────────────────────────────────── VBE/AI SDK v1.03 VAISDK.EXE 388K Video Electronic Standards Association 1994 ftp.wi.leidenuniv.nl:/pub/audio/programming TEXT, C ──────────────────────────────────────────────────────────────────────────── Virtual DMA Specification (VDS) PW0519.ZIP 47K John Hagerson of Microsoft 1992 ftp.microsoft.com::Softlib/MSLFILES TEXT, WORD ──────────────────────────────────────────────────────────────────────────── SOURCE ──────────────────────────────────────────────────────────────────────────── SoundBlaster Freedom Project v3.0 SBF3.ZIP 85K Jeff Bird, Christopher Box 1994 x2ftp.oulu.fi::pub/msdos/programming/music C, ASM ──────────────────────────────────────────────────────────────────────────── SoundBlaster Programming v1.0 SBPROG10.ZIP 36K Christopher Box 1993 x2ftp.oulu.fi::pub/msdos/programming/music C++, ASM ──────────────────────────────────────────────────────────────────────────── SoundX SoundBlaster Library SOUNDX.ZIP 32K Peter Sprenger 1993 x2ftp.oulu.fi::pub/msdos/programming/music C, ASM ──────────────────────────────────────────────────────────────────────────── SNDBLST v4.0 SNDBLST4.ZIP 96K David Welch 1993 x2ftp.oulu.fi::pub/msdos/programming/music C ──────────────────────────────────────────────────────────────────────────── NEWSGROUPS ──────────────────────────────────────────────────────────────────────────── SoundBlaster Programming alt.sb.programmer Soundcard Technical Discussion comp.sys.ibm.pc.soundcard.tech comp.sys.ibm.pc.soundcard.misc ──────────────────────────────────────────────────────────────────────────── ============================================================================== CONTACT ADDRESSES ------------------------------------------------------------------------------ André Baresel baresel@informatik.hu-berlin.de (Internet ) Cyder of Green Apple André Baresel (Snailmail) Hans-Grade-Ring 5 14480 Potsdam Germany Craig Jackson Craig.Jackson@launchpad.unc.edu (Internet ) Craig Jackson (Snailmail) 119 Penwood Drive Cary, North Carolina 27511 United States of America